ASIC Design Verification Engineer | UVM | Exp. 8+ years

Cisco · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:15 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2006926

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected role description

Join our team as a ASIC Design Verification Engineer, where you will define, design, and verify ASIC and subsystems for Cisco platforms. You will architect and develop DV infrastructure, develop test plans, and ensure RTL quality. Ideal candidates have significant ASIC verification experience and expertise in UVM/System Verilog.

Collected experience requirement

8+ years