Design Verification Lead, Google Cloud
Google · Bangalore
Source and collection record
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Collected role description
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy . Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
Collected minimum qualification
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.; 10 years of experience with hardware verification languages (System Verilog/Specman), design verification methodologies, and chip design flow.; Experience creating detailed chip or subsystem design verification strategies and plans.; Experience leading design verification teams through the full cycle, from concept to delivery.
Collected preferred qualification
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.; Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).; Experience with verification techniques and the full verification life cycle.; Experience with performance verification of ASICs and ASIC components.; Experience with ASIC standard interfaces and memory system architecture.; Experience with multiple SOC projects/cycles in three or more products.
Collected experience requirement
10 years of experience with hardware verification languages (System Verilog/Specman), design verification methodologies, and chip design flow.