PNR | Careers | Neurealm

Ignitarium · Chennai

Source and collection record

Last observed by our collector: 8 October 2026 at 11:33 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: ignitarium-pnr-chennai-india-2026-10-08

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

RESPONSIBILITIES: Perform full chip / block-level Physical Design (PNR) activities Work on floorplanning, placement, CTS (Clock Tree Synthesis), routing, and optimization Handle timing closure Service AI-as-a-Service AI-powered SDLC Enterprise AI Adoption Engineering Silicon Design Embedded AI-powered Modernization Digital Platform Engineering AI-powered SDLC Robotics Data Data Overview Data Engineering Data Migration Data Visualization & Analytics Master Data Management & Governance Run Ops AI Led ITOps Cybersecurity Intelligent Automation Industries Semiconductor Automotive Healthcare BFSI Technology Telecom Industrial Global Capability Centers (GCCs) Neu GAIN About Us Company Leadership Life at Neurealm Awards & Recognitions Events Press Releases Partners Careers Contact Us search Menu Job Description Back PNR Job Posted On 08-10-2026 18:57:34 Company Group Neurealm SEAD India --> Department PD (Physical Design) --> Employee Type Full Time Employee --> Designation PNR --> Job Code Job_304082 Experience Required --- Location Chennai, Tamil Nadu, India (WAC_007) Bangalore, Karnataka, India (WAC_003) Kochi, Kerala, India (WAC_004) Job Summary Job RESPONSIBILITIES: Perform full chip / block-level Physical Design (PNR) activities Work on floorplanning, placement, CTS (Clock Tree Synthesis), routing, and optimization Handle timing closure and congestion analysis Perform physical verification checks (DRC, LVS, IR drop, EM analysis) Collaborate with RTL, STA, and DFT teams for design convergence Work on low power techniques and multi-voltage designs Ensure design meets performance, power, and area (PPA) targets Required Skills: Strong experience in Place & Route (PNR) flow Hands-on with tools like Cadence Innovus / Synopsys ICC2 Good knowledge of STA concepts Experience in advanced nodes (7nm / 5nm / 3nm is a plus) Understanding of physical verification (DRC/LVS) Scripting knowledge ( TCL / Python ) is an added advantage

Collected experience requirement

- Years