ASIC Front-end Design engineer

HPE · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:31 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 1207305

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

We are currently hiring an ASIC Front-end Design Engineer to define and architect high-performance blocks for advanced networking ASICs. Collaborate with system design teams and contribute to high-speed, complex system development. Ideal for candidates with strong Verilog RTL coding skills and experience in ASIC design. We are currently hiring an ASIC Front-end Design Engineer to define and architect high-performance blocks for advanced networking ASICs. Collaborate with system design teams and contribute to high-speed, complex system development. Ideal for candidates with strong Verilog RTL coding skills and experience in ASIC design.