Senior ASIC Design Engineer

HPE · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:31 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 1210202

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Collected role description

We are currently hiring a Senior ASIC Design Engineer to define and architect high-performance blocks for advanced networking ASICs. You will collaborate with verification and physical design teams, focusing on micro-architecture and logic design. Ideal candidates possess strong Verilog RTL coding skills and experience in ASIC design for networking protocols. We are currently hiring a Senior ASIC Design Engineer to define and architect high-performance blocks for advanced networking ASICs. You will collaborate with verification and physical design teams, focusing on micro-architecture and logic design. Ideal candidates possess strong Verilog RTL coding skills and experience in ASIC design for networking protocols.