Verification Lead

Logic Fruit Technologies · Gurgaon

Source and collection record

Last observed by our collector: 8 October 2026 at 11:41 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 10000001-0000-4000-8000-000000000003

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected minimum qualification: ### Education & Experience - **Education:** B.Tech / M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), or related field. - **Experience:** 6 to 12 years of core digital design verification experience with proven team leadership track record. ### Core Technical Competencies - **Verification Methodologies:** Strong mastery of SystemVerilog (SV), OOP/classes, and Universal Verification Methodology (UVM). - **Constrained Randomization & Coverage:** Deep expertise in constrained-random stimulus generation, assertions (SVA), and functional coverage closure. - **High-Speed Protocols:** Mandatory knowledge of one or more high-speed protocols (PCIe, CXL, Ethernet, DisplayPort, etc.). - **On-Chip Bus Interfaces:** Thorough understanding of on-chip bus architectures including AXI, AHB, APB, etc. - **Execution & Soft Skills:** Strong project planning, communication, and interpersonal skills to collaborate effectively with cross-functional teams and international clients.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

We are looking for a skilled Verification Lead to manage verification teams across high-complexity ASIC and FPGA IP projects, defining robust UVM testbench architectures and driving functional verification closure. Lead verification team on multiple projects, architect UVM testbenches, and drive coverage closure across high-speed protocols. ### Technical Leadership & Project Delivery - **Multi-Project Team Leadership:** Lead and mentor verification teams across concurrent projects, ensuring rigorous execution and delivery against committed milestones. - **Stakeholder Collaboration:** Partner closely with clients, sales/marketing, project managers, and RTL design teams to plan verification scope, timelines, and deliverables. - **Technical Guidance & Mentorship:** Provide hands-on technical direction to team members across all verification phases, from test plan creation to coverage sign-off. - **Protocol & Scenario Planning:** Guide team members on protocol specifications, testbench architecture, and planning/execution of complex error-related test scenarios. ### Quality & Verification Closure - **Code Reviews:** Enforce strict verification code quality standards and reusable design patterns through structured peer code reviews. - **Verification Architectures:** Drive development of comprehensive UVM-based verification plans, constrained-random testbenches, and functional coverage models. ### Education & Experience - **Education:** B.Tech / M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), or related field. - **Experience:** 6 to 12 years of core digital design verification experience with proven team leadership track record. ### Core Technical Competencies - **Verification Methodologies:** Strong mastery of SystemVerilog (SV), OOP/classes, and Universal Verification Methodology (UVM). - **Constrained Randomization & Coverage:** Deep expertise in constrained-random stimulus generation, assertions (SVA), and functional coverage closure. - **High-Speed Protocols:** Mandatory knowledge of one or more high-speed protocols (PCIe, CXL, Ethernet, DisplayPort, etc.). - **On-Chip Bus Interfaces:** Thorough understanding of on-chip bus architectures including AXI, AHB, APB, etc. - **Execution & Soft Skills:** Strong project planning, communication, and interpersonal skills to collaborate effectively with cross-functional teams and international clients.

Collected minimum qualification

### Education & Experience - **Education:** B.Tech / M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), or related field. - **Experience:** 6 to 12 years of core digital design verification experience with proven team leadership track record. ### Core Technical Competencies - **Verification Methodologies:** Strong mastery of SystemVerilog (SV), OOP/classes, and Universal Verification Methodology (UVM). - **Constrained Randomization & Coverage:** Deep expertise in constrained-random stimulus generation, assertions (SVA), and functional coverage closure. - **High-Speed Protocols:** Mandatory knowledge of one or more high-speed protocols (PCIe, CXL, Ethernet, DisplayPort, etc.). - **On-Chip Bus Interfaces:** Thorough understanding of on-chip bus architectures including AXI, AHB, APB, etc. - **Execution & Soft Skills:** Strong project planning, communication, and interpersonal skills to collaborate effectively with cross-functional teams and international clients.

Collected experience requirement

6-12yrs