Project Lead - FPGA

Logic Fruit Technologies · Gurgaon

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Last observed by our collector: 8 October 2026 at 11:41 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 10000001-0000-4000-8000-000000000004

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Collected minimum qualification: ### Experience & Technical Background - **Experience:** 6+ years of experience, including successful completion of FPGA-based projects. - **HDL Coding:** Coding experience in VHDL and/or Verilog is mandatory. - **FPGA Platforms:** Experience targeting Xilinx (UltraScale+, Zynq, Versal) and/or Altera/Intel (Agilex, Quartus) FPGAs required. - **EDA Tools:** Familiarity with tools like ModelSim, QuestaSim, Xilinx Vivado, PlanAhead, Altera Quartus, etc. is required. - **Debugging Instrumentation:** Familiarity with debugging tools like Chipscope, Signal Tap, Logic Analyzer, Oscilloscopes, and FPGA Editor. - **Clock Domain Architectures:** Implementation of designs with multiple clock domains is required. - **Coding Styles:** Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed. - **Appreciated Experience:** - Experience in RTL implementation of DSP algorithms. - Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, UART, I2C, SPI.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

As FPGA Design Lead, your role will be to manage and lead design engineers to implement complex FPGA IPs and FPGA-based digital designs. You should be able to understand project requirements and define architecture/micro-architecture with proper documentation, guiding the team for system development, verification, debugging, and HW/SW integration. Manage and lead design engineers to implement complex FPGA IPs and digital designs from specification to system integration. ### Architecture & Design Implementation - **RTL Development:** Develop production-quality RTL code in VHDL/Verilog to implement FPGA-based digital designs, working from specification stage through system integration. Projects range from mid to multi-million gates. - **High-Speed Protocol Logic:** Design logic for latest generation high-speed serial protocols including PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, DSP pipelines, and control logic (bus interfaces and state machines). - **Requirements to Architecture:** Understand customer requirements and product definition; define architecture and detailed design specifications based on requirements and various trade-offs. - **Micro-Architecture & Coding:** Micro-architecture design and coding of assigned modules in VHDL/Verilog. ### Verification, Timing Closure & System Bring-Up - **Testbench Development:** Write testbenches for verifying design for complete scenario and corner-case coverage. - **FPGA Implementation:** Implementation of the design for porting on FPGA after required optimization based on available resources and timing closure requirements. - **HW/SW Integration & Debug:** Lead FPGA debugging on hardware boards, logic analyzers, and HW/SW integration. ### Experience & Technical Background - **Experience:** 6+ years of experience, including successful completion of FPGA-based projects. - **HDL Coding:** Coding experience in VHDL and/or Verilog is mandatory. - **FPGA Platforms:** Experience targeting Xilinx (UltraScale+, Zynq, Versal) and/or Altera/Intel (Agilex, Quartus) FPGAs required. - **EDA Tools:** Familiarity with tools like ModelSim, QuestaSim, Xilinx Vivado, PlanAhead, Altera Quartus, etc. is required. - **Debugging Instrumentation:** Familiarity with debugging tools like Chipscope, Signal Tap, Logic Analyzer, Oscilloscopes, and FPGA Editor. - **Clock Domain Architectures:** Implementation of designs with multiple clock domains is required. - **Coding Styles:** Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed. - **Appreciated Experience:** - Experience in RTL implementation of DSP algorithms. - Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, UART, I2C, SPI.

Collected minimum qualification

### Experience & Technical Background - **Experience:** 6+ years of experience, including successful completion of FPGA-based projects. - **HDL Coding:** Coding experience in VHDL and/or Verilog is mandatory. - **FPGA Platforms:** Experience targeting Xilinx (UltraScale+, Zynq, Versal) and/or Altera/Intel (Agilex, Quartus) FPGAs required. - **EDA Tools:** Familiarity with tools like ModelSim, QuestaSim, Xilinx Vivado, PlanAhead, Altera Quartus, etc. is required. - **Debugging Instrumentation:** Familiarity with debugging tools like Chipscope, Signal Tap, Logic Analyzer, Oscilloscopes, and FPGA Editor. - **Clock Domain Architectures:** Implementation of designs with multiple clock domains is required. - **Coding Styles:** Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed. - **Appreciated Experience:** - Experience in RTL implementation of DSP algorithms. - Experience in development of PCIe, USB, Ethernet transceivers, DDRx, ADC, DAC, AMBA-AXI, SRAM, UART, I2C, SPI.

Collected experience requirement

6+ Years