FPGA RTL Engineer

We seek a skilled and delivery-focused FPGA Engineer to develop RTL code and implement FPGA-based digital designs, working from specification stage through to system integration. Projects will range from mid-scale to multi-million gate designs involving the latest generation of high-speed serial protocols, DSP pipelines, and control logic — delivered on time and to production quality standards. Develop synthesizable RTL code, high-speed serial protocols, and implement FPGA-based digital designs from specification to system integration. ### 1. Requirements Understanding & Architecture Definition #### Customer Requirements & Product Definition - Engage with product and systems teams to thoroughly understand design intent before committing to implementation. - Study and interpret customer requirements and product definition documents; raise clarifications and track requirement changes. - Translate system-level requirements into block-level technical constraints: gate count budget, clock frequencies, interface bandwidths, and latency targets. - Participate in customer-facing or internal technical reviews to align on scope, schedule, and design assumptions. #### Architecture & Detailed Design Specification - Author micro-architecture documents: block diagrams, state machine descriptions, data path sketches, interface signal definitions, and timing budgets. - Evaluate architectural trade-offs: soft IP vs. hard IP, VHDL vs. Verilog coding approach, pipeline depth vs. resource utilization, and clock domain strategies. - Define resource estimates (LUT, FF, BRAM, DSP, SERDES) and present architecture proposals at design review gates. - Document all design decisions and rationale in the engineering design record for traceability through to production. ### 2. RTL Micro-Architecture & Coding #### Micro-Architecture & Module Coding - Code production-quality RTL in VHDL and/or Verilog: state machines, data path pipelines, control logic, FIFOs, arbiters, and bus interfaces. - Implement high-speed serial protocol logic covering PCIe Gen5/Gen6, USB 3.2, Ethernet 10G/25G/100G, Aurora, and AMBA-AXI interconnects. - Design digital signal processing blocks: FIR/IIR filters, FFT/IFFT pipelines, decimation/interpolation chains, and fixed-point arithmetic units. - Implement memory interface controllers: DDRx, SRAM, and cache management logic optimized for FPGA memory architecture. - Code peripheral and control interfaces: UART, I2C, SPI, USB, and interrupt controllers with software-accessible register maps. #### Coding Standards & Multiple Clock Domains - Apply FPGA-appropriate coding styles: synchronous resets, registered outputs, one-hot FSM encoding, and inference of FPGA primitives (BRAM, DSP, SRL). - Follow design-for-verification and design-for-implementation guidelines: avoid combinational loops, latches, and uncontrolled clock gating. - Design clock domain crossing (CDC) structures: synchronizers, async FIFOs, handshake protocols, and multi-bit CDC strategies. - Use CDC analysis tools (Mentor CDC, Cadence Conformal CDC) to verify crossing structures before synthesis. ### 3. Verification & Functional Sign-Off #### Testbench Development & Coverage Closure - Develop self-checking testbenches in VHDL / SystemVerilog: stimulus generators, response monitors, scoreboards, and coverage collectors. - Write directed tests for nominal operation and constrained-random tests targeting corner cases, protocol violations, and error injection scenarios. - Achieve functional coverage targets: line coverage, branch coverage, FSM state/transition coverage, and toggle coverage prior to sign-off. - Run RTL and gate-level simulations in ModelSim / QuestaSim / Xcelium; analyze waveforms and debug failures to root cause. - Verify PCIe, USB, Ethernet, AXI, and JESD204B/C interface logic using BFMs and VIP. ### 4. FPGA Implementation, Timing Closure & Hardware Debugging #### Implementation Flow & Timing Closure - Run synthesis in Xilinx Vivado / PlanAhead and Altera Quartus Prime; analyze utilization, timing, and power reports after each run. - Apply physical constraints: pin assignments, I/O standards, Pblock floorplan constraints, and LOC/BEL directives for performance-critical paths. - Author SDC/XDC timing constraints: create_clock, set_input_delay, set_output_delay, set_multicycle_path, and set_false_path directives. - Analyze timing reports and apply optimizations: pipeline register insertion, logic replication, carry chain usage, and DSP/BRAM packing. #### Hardware Debugging & Integration - Debug FPGA designs on hardware using Chipscope Pro / Vivado Hardware Manager (Xilinx) and Signal Tap Logic Analyzer (Altera/Intel). - Use external debug equipment: oscilloscopes, logic analyzers, protocol analyzers, and BERTs to isolate signal integrity and functional failures. - Support HW/SW integration: validate register map access, interrupt routing, DMA data transfers, and driver handshake sequences with embedded software. ### Education & Experience - **Education:** Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline. - **Experience:** 2 – 15+ years of hands-on FPGA engineering experience including successful completion of at least one FPGA-based product or platform project. - **Project Track Record:** Must have contributed to a complete FPGA project lifecycle — from RTL coding through implementation and hardware bring-up. Simulation-only or purely academic experience does not qualify. ### Technical Expertise — Core Requirements #### RTL Design — Must Have - Coding experience in VHDL and/or Verilog is mandatory — ability to write clean, synthesizable RTL for data path, control, and interface blocks. - Thorough understanding of FPGA-appropriate coding styles: synchronous design, FSM encoding, BRAM/DSP/SRL inference, and registered output disciplines. - Demonstrated understanding of speed vs. density trade-offs and how RTL coding choices directly affect synthesis and P&R quality of results (QoR). - Experience designing with multiple clock domains: CDC structures, async FIFOs, synchronizers, and clock domain classification for constraints. #### FPGA Devices & Tools — Must Have - Experience targeting Xilinx and/or Altera FPGAs is required — familiarity with UltraScale+, Zynq, Versal (Xilinx/AMD) or Agilex, Stratix 10 (Intel/Altera). - Proficiency with EDA tools: Xilinx Vivado / PlanAhead and/or Altera Quartus Prime for synthesis, P&R, timing analysis, and bitstream generation. - Simulation tool experience: ModelSim, QuestaSim, or equivalent — ability to run regressions, analyze waveforms, and debug simulation failures. - Hardware debug tool proficiency: Chipscope Pro, Vivado Hardware Manager (Xilinx) and/or Signal Tap Logic Analyzer (Altera); familiarity with logic analyzers, oscilloscopes, and protocol analyzers. #### High-Speed Serial Interfaces — Core - Practical RTL implementation experience with high-speed serial protocols: PCIe Gen4/5, USB 3.2, Ethernet 10G/25G/100G, or equivalent. - Experience with AMBA-AXI / AXI4-Stream interconnect fabric for on-chip bus integration and DMA data flow. - Familiarity with transceiver / GT architecture: link training, channel bonding, and protocol initialization sequences. #### Memory & Peripheral Interfaces — Core - Experience with memory interfaces: DDRx controller integration, timing constraints, and burst access optimization. - Implementation experience with peripheral interfaces: UART, I2C, SPI, or equivalent register-based control interfaces. - Familiarity with ADC/DAC interfaces for data acquisition and signal processing applications. ### Appreciated Experience & Advanced Skills - **DSP on FPGA:** Experience in RTL implementation of DSP algorithms: FIR/IIR filters, FFT, decimation/interpolation, and fixed-point arithmetic pipelines. Understanding of DSP slice usage (DSP48E2 / DSP58). - **Advanced Interfaces:** Development experience with PCIe Gen5/Gen6, CXL, 200G/400G Ethernet, or JESD204B/C for high-bandwidth platform designs. - **AI/ML on FPGA:** Exposure to Vitis AI / Versal DPU for AI/ML inference deployment on FPGA platforms. ### Engineering Competencies - **Technical Ownership:** Proven ability to own assigned RTL modules from specification through verification sign-off and implementation closure with minimal supervision. - **Execution Excellence:** Delivers RTL blocks, testbenches, and implementation results on committed schedule; flags risks early with proposed mitigations. - **Collaboration & Communication:** Communicates design decisions, trade-offs, and implementation risks clearly in design reviews; writes comprehensive documentation.