Director / Sr Director - FPGA & HW Engineering

We seek a technical engineering leader to drive product innovation, architectural excellence, and execution discipline across our FPGA-based hardware platforms. This is a pure engineering leadership role — you will define products, architect solutions, lead technical teams, and deliver world-class FPGA platforms on budget and on schedule. Lead product innovation, architectural excellence, and multi-site execution across next-generation FPGA hardware platforms reporting directly to the CEO. ### 1. Product Definition & Technical Leadership #### System Architecture & Product Vision - Define end-to-end architecture for FPGA-based platforms — from silicon selection and IP strategy to board design, firmware, and system validation. - Translate market requirements into technical specifications and multi-year product roadmaps. #### Innovation Leadership - Drive product-level innovation in: - Heterogeneous FPGA architectures (AMD Versal, Altera Agilex) - Deterministic AI/ML inference for edge computing - High-speed interfaces (PCIe Gen6/7, CXL, 200G/400G/800G Ethernet, PQC, etc.) #### Technical Decision Authority - Own all major technical decisions: FPGA device selection, IP vs. custom RTL trade-offs, verification strategy, toolchain selection, and design methodology standards. ### 2. Engineering Execution & Delivery #### End-to-End Product Delivery - Lead cross-functional engineering teams through full product lifecycle: - RTL design, synthesis, place & route, timing closure - Board design (high-speed digital, power integrity, thermal) - Firmware and embedded software - System integration and performance validation - Certification and compliance #### Execution Discipline & Risk Management - Establish and enforce engineering rigor: design reviews, verification closure (SystemVerilog/UVM), release gates, and post-silicon validation protocols. - Manage NRE budgets and ensure predictable delivery against committed schedules. - Identify and mitigate technical risks early: silicon errata workarounds, timing closure challenges, signal integrity issues, thermal constraints, and supply chain dependencies. ### 3. Organization Building & Leadership #### Multi-Site Engineering Leadership - Unify Gurugram and Bangalore engineering teams under common design methodologies, verification frameworks, and release processes. - Build a culture of technical excellence, ownership, and accountability. #### Talent Development & Scaling - Build and mentor the next generation of technical leaders; create clear technical career paths from Senior Engineer through Principal/Fellow levels. - Maintain >=90% retention of Senior Staff+ talent through technical mentorship, challenging problems, IP co-ownership, and a culture that values deep technical expertise. - Scale the engineering organization from 150 to 200+ engineers over 24 months while maintaining quality, velocity, and culture. ### Education & Executive Experience - **Education:** Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline. - **Experience:** 18+ years in FPGA/hardware engineering, including 8+ years leading engineering teams of 100+ engineers. - **Product Delivery Track Record:** Must have led engineering teams that delivered >=2 FPGA-based products from architecture through volume production (>500 units shipped). Pure design services or consulting experience does not qualify. ### Technical Expertise — Core Requirements #### FPGA Mastery - Deep expertise with AMD/Xilinx (Versal, UltraScale+) and/or Intel/Altera (Agilex, Stratix) device families. - Advanced proficiency with Vivado, Vitis, Quartus, and High-Level Synthesis (HLS). - Hands-on experience with complex FPGA architectures: AI Engines, DSP slices, high-speed transceivers, DDR controllers. #### AI/ML on FPGA - Practical experience deploying AI/ML inference on FPGAs (Vitis AI, Versal DPU, or custom accelerators). - Understanding of model quantization, DPU vs custom RTL trade-offs, and deterministic latency optimization. - Experience with vision processing, sensor fusion, or real-time packet processing workloads. #### High-Speed Digital Design & Verification - Proven delivery of platforms with PCIe Gen5/6, 100G+ Ethernet, or RF-ADC/DAC. - Signal integrity, timing closure, and power integrity at advanced nodes. - Strong command of SystemVerilog/UVM, constrained-random verification, and coverage-driven methodologies. - Experience with HW/SW co-verification, emulation platforms, and FPGA prototyping. #### Board-Level Systems - Understanding of complete system design: power architecture, thermal management, PCB layout constraints for high-speed signals. - Experience with ruggedized or embedded systems for defense/aerospace applications. ### Leadership Competencies - **Technical Leadership at Scale:** Proven ability to lead 100+ engineer organizations across multiple sites in India. Experience unifying distributed teams under common methodologies & quality standards. - **Execution Excellence:** Demonstrated ability to deliver complex hardware products on time and within budget. Experience managing multi-year product roadmaps with 8-12 month development cycles. - **Communication & Influence:** Ability to translate complex technical architectures into clear roadmaps. Comfortable presenting technical designs to customers, partners, and executives.