SI/PI Engineer at LTTS

LTTS · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:41 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 535101

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Collected role description

• Perform channel modeling, extraction, and eye analysis for high-speed interfaces. • Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards. • Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR. • Model, analyze and provide recommendations on board PDN. • Perform AC/DC droop analysis, target impedance profiling to ensure clean power delivery to high-current ASICs, So Cs, and FPGAs. • Collaborate with Hardware and ECAD teams to optimize signal integrity and power integrity performance. • Provide design guidelines balancing both SI and PI constraints. • Generate technical reports and provide design recommendations based on simulation results. • Perform channel modeling, extraction, and eye analysis for high-speed interfaces. • Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards. • Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR. • Model, analyze and provide recommendations on board PDN. • Perform AC/DC droop analysis, target impedance profiling to ensure clean power delivery to high-current ASICs, So Cs, and FPGAs. • Collaborate with Hardware and ECAD teams to optimize signal integrity and power integrity performance. • Provide design guidelines balancing both SI and PI constraints. • Generate technical reports and provide design recommendations based on simulation results. Job Description • Perform channel modeling, extraction, and eye analysis for high-speed interfaces. • Conduct pre-layout and post-layout SI simulations to ensure compliance with interface standards. • Analyze crosstalk, reflections, jitter, insertion loss, return loss and TDR. • Model, analyze and provide recommendations on board PDN. • Perform AC/DC droop analysis, target impedance profiling to ensure clean power delivery to high-current ASICs, So Cs, and FPGAs. • Collaborate with Hardware and ECAD teams to optimize signal integrity and power integrity performance. • Provide design guidelines balancing both SI and PI constraints. • Generate technical reports and provide design recommendations based on simulation results. Job Requirement • Strong understanding of signal integrity and power integrity concepts for high-speed serial and memory interfaces. • Hands-on experience with: Ansys HFSS, Altium Designer, Ansys Siwave, Siemens hyperlynx 2D & 3D • Familiarity with JEDEC, LPDDR4/LPDDR5, PCIe 4/5, GMSL, FPD -Link, MIPI-CSI, USB, Ethernet and other automotive standards. • Ability to perform board level timing analysis using tools. • Strong analytical and problem-solving skills with good communication and documentation skills.