DV Engineer at LTTS

LTTS · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:41 pm IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 531758

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected role description

Design Verification (DV) Engineer tests and validates integrated circuit and semiconductor designs to ensure they are bug-free and meet functional specifications before manufacturing. Key aspects include System Verilog, UVM (Universal Verification Methodology), and test planning Design Verification (DV) Engineer tests and validates integrated circuit and semiconductor designs to ensure they are bug-free and meet functional specifications before manufacturing. Key aspects include System Verilog, UVM (Universal Verification Methodology), and test planning Job Description Design Verification (DV) Engineer tests and validates integrated circuit and semiconductor designs to ensure they are bug-free and meet functional specifications before manufacturing. Key aspects include System Verilog, UVM (Universal Verification Methodology), and test planning Job Requirement DV Engineer