Sr. RTL Design Engineer

Pixxel · Bangalore

Source and collection record

Last observed by our collector: 8 October 2026 at 11:58 pm IST. This is not a manual review or a confirmation from the employer.

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 2 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

Role: Sr. RTL Engineer Employment Type: Full Time Educational Qualification: Bachelor's degree in Electrical Engineering, Computer Science, or a related field.Work Experience: 4-6 years of industry experience. Role Description: Pixxel is widely considered to be one of the fastest-growing aerospace start-ups. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of earth observation. Come join our Avionics team and help us build future architectures that will continue to drive us forward in the field. Responsibilities & Duties: <ul style="margin-bottom: 0px; padding-inline-start: 48px;"><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Participate in next-generation system architecture – a full system effort spanning mission planning, software, hardware, and other sub-systems.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Develop custom IP for new features of the Pixxel camera payload and satellite bus.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Understand the design requirements, establish the design infrastructure, support verification engineers, and test the correctness of the design.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Realize high-reliability digital design targeting state-of-the-art Xilinx FPGAs.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Participate in conceptual design studies of new spacecraft.</li></ul>Desirable Skills & Certifications:<ul style="margin-bottom: 0px; padding-inline-start: 48px;"><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Comfortable working with Xilinx Vivado Design Suite.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Experience with external memories (SSD, FLASH, etc.); high-speed transceivers for protocols such as PCIe, SATA; and memory-mapped interfaces such as AXI, Wishbone, Avalon.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Using advanced design methodologies like Hierarchical Design.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Experience using lab equipment: high-speed oscilloscopes, logic and protocol analyzers, spectrum analyzers, etc.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Experience with schematic design and board bring-up is a plus point. </li></ul>Would be great if you have<ul style="margin-bottom: 0px; padding-inline-start: 48px;"><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">A Bachelor’s Degree in EE, CS or CE (or a related field) with at least 2+ years of relevant experience or an Advanced Degree (Masters or PhD).</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Excellent knowledge of hardware description languages (Verilog/System Verilog/VHDL).</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Strong understanding of computer architecture and logic design, and serial interfaces – SPI, I2C, LVDS, etc.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Solid understanding of timing principles, including clock domain crossing and timing closure.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Experience with FPGA tools (e.g Vivado) and HDL Simulation Tools (ModelSim).</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Strong debugging and analytical skills.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Strong communication skills and the ability to work in a small team are a huge plus.</li><li dir="ltr" aria-level="1" style="font-size: 11pt; font-family: Arial, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; vertical-align: baseline; white-space: pre;">Solid programming skills (C / C++, Python, Matlab).</li></ul>Candidate Acumen: A strong desire to work in an unstructured, high-growth, fast-paced start-up environment>Benefits: Health insurance coverage Unlimited leaves & flexible working hours Role-based remote work and work-from-home benefit Relocation assistance Professional Mental Wellness services Creche facility for primary caregivers (limited to India) Employee Stock Options for all hires<h2 dir="ltr" style="margin-top: 0pt; margin-bottom: 0pt; line-height: 1.32; text-align: justify; padding: 6pt 0pt 8pt;">About Pixxel</h2>Pixxel is a space technology company, building a constellation of hyperspectral earth imaging satellites and the analytical tools to mine insights from that data. We are on a mission to build a health monitor for the planet through a constellation of cutting-edge hyperspectral small satellites.  Pixxel’s constellation is designed to provide global coverage every 24 hours to detect, monitor, and predict global phenomena across agriculture, mining, environmental, national security, and energy use cases. This unique hyperspectral capability will be the key to unearth underlying, unseen problems that are invisible to satellites in orbit today. Pixxel has collaborated with prominent organizations such as the US National Reconnaissance Office, the National Geospatial Intelligence Agency, US Space Force, the national labs, NASA JPL, SpaceX, the Indian Space Research Organization, among other leaders in the space and earth monitoring community.  Recently, Pixxel successfully raised over $36 Million in its Series B funding round, with participation from new investors like Google, alongside existing investors, bringing the company's total venture funding to over $71 Million. To learn more, visit us at <a href="https://www.pixxel.space/"><span style="font-size: 10pt; font-family: Inter, sans-serif; color: rgb(0, 0, 0); background-color: transparent; font-variant: normal; text-decoration: underline; text-decoration-skip-ink: none; vertical-align: baseline; white-space: pre-wrap;">https://www.pixxel.space</a>. CulturePixxel enables our employees to express their passions to work on world-changing solutions.  Pixxel offers an environment where employees are appreciated for their best qualities, challenged to grow, and trained to advanced, all while having fun!Central to our employee-first ethos is a commitment to ensuring that every team member feels valued and heard. We nurture a healthy and supportive work environment where we prioritize well-being and growth in all aspects of life <a href="https://www.notion.so/pixxelspacetech/Pixxel-in-Media-92a5072f085e4300a0defa1ba2d37149"><span style="font-size: 10pt; font-family: Inter, sans-serif; color: rgb(17, 85, 204); background-color: transparent; font-variant: normal; text-decoration: underline; text-decoration-skip-ink: none; vertical-align: baseline; white-space: pre-wrap;">Link to Pixxel in Media</a><div> </div><ul class="Pay Rate Group"> </ul>

Collected experience requirement

4 - 6 Years