Lead Engineer - RISC

Quest Global · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:00 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: P-123029

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Collected role description

We are recruiting a Lead Engineer - RISC to design and implement UVM/SystemVerilog verification environments, create test plans, and drive code coverage. The role involves collaborating with cross-functional teams and verifying system protocol behaviour. Ideal for candidates with strong expertise in verification environments and system integration.