senior engineer- DV

Quest Global · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:00 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: P-118347

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected role description

We are recruiting a Senior Engineer – DV to drive full chip verification and OVM/UVM methodology, focusing on ARM-based SoC verification. The role requires expertise in System Verilog and scripting languages, with experience in PCIe, USB, and networking. Ideal for candidates with 3–5 years’ experience in SOC and code coverage verification.

Collected experience requirement

3-5 years