Design Verification Engineer

Quest Global · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:00 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: P-117624

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

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Collected role description

Exciting opportunity for a Design Verification Engineer to ensure the functional correctness and quality of complex IP blocks and subsystems. Key responsibilities include developing and maintaining UVM-based testbench environments and collaborating with architects and RTL designers. Ideal for candidates with strong SystemVerilog expertise and hands-on ASIC/SoC design verification experience.

Collected experience requirement

3+ years