SOC Engineering Senior Staff Engineer (STA)

Learn more about applying for SOC Engineering Senior Staff Engineer (STA) at Synopsys Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 10/05/2026 Category Engineering Hire Type Employee Job ID 19120 Remote Eligible No Date Posted 10/05/2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and execution-focused Static Timing Analysis (STA) engineer with strong fundamentals in timing closure and signoff methodologies. You bring 8+ years of hands-on experience in STA and timing/power closure for advanced nodes (e.g., 16/12/10/7nm; exposure to 5nm is a plus). You are comfortable owning key timing deliverables for blocks and contributing to full-chip closure in collaboration with physical design, synthesis, and verification teams. You have solid experience across the timing closure lifecycle—constraints development and validation, STA signoff, power analysis, and ECO support—and you enjoy solving complex timing issues under aggressive schedules. You communicate clearly, work effectively with global teams, and are motivated to improve productivity through scripting/automation (TCL/Python/Perl). What You’ll Be Doing: Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes. Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams. Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage. Run and analyze power signoff/support flows (Prime Power / PT-PX) and correlate timing/power impacts of ECOs. Support timing and power ECO generation, and validate fixes through signoff checks and regressions. Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates). Use Synopsys tools such as Prime Time, Prime Power/PT-PX, Prime Closure/Tweaker (as applicable) to meet PPA targets. Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality. Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed. The Impact You Will Have: Enable predictable and high-quality timing closure for high-performance, low-power silicon. Improve first-pass success through robust constraints, clean signoff, and disciplined closure practices. Strengthen team execution by contributing to repeatable STA flows, automation, and cross-team alignment. Support successful project milestones through timely analysis, crisp communication, and ownership of deliverables. What You’ll Need: Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field. 8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred). Strong hands-on experience in: Constraints development/validation (SDC) STA signoff across modes/corners, including MMMC concepts Timing closure debugging and ECO validation Power analysis/support (Prime Power / PT-PX exposure preferred) Proficiency with Synopsys tools such as Prime Time (required); Prime Power/PT-PX, Prime Closure/Tweaker (preferred). Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., Star RC), and signoff correlation (preferred). Strong scripting skills in TCL (required) and Python/Perl (preferred). Understanding of low-power and high-frequency design considerations (UPF awareness is a plus). Who You Are: Self-driven, accountable, and comfortable working with minimal supervision on defined deliverables. Strong analytical and debugging skills with attention to detail. Clear communicator and effective collaborator across design, PD, and verification. Open to learning, improving flows, and sharing knowledge within the team. The Team You’ll Be A Part Of: You’ll join a team of backend and STA engineers focused on delivering robust timing and power closure solutions for leading silicon designs. The team values technical rigor, collaboration, and continuous improvement—working closely with experts across domains to help customers achieve their silicon goals. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share details on compensation and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email Linked In X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you