Digital Design, Senior Engineer

Learn more about applying for Digital Design, Senior Engineer at Synopsys Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 09/22/2026 Category Engineering Hire Type Employee Job ID 18479 Remote Eligible No Date Posted 09/22/2026 ASIC Digital Design Engineer, Senior We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation. You Are: You are a Senior ASIC Digital Design Engineer who delivers high-quality RTL for complex PCIe IP. You take a spec or micro-architecture, implement it cleanly, debug it thoroughly, and stand behind the block you own. You have proven digital design experience on So C or IP, ideally high-speed interfaces. You understand clocks, resets, state machines, pipelines, and synthesizable coding practice. PCIe experience is a strong plus; equivalent protocol or data-path experience is welcome. You work closely with Staff and Principal engineers for your assigned subsystem features. You contribute in reviews, write maintainable RTL, and help verification reproduce and close issues. What You'll Be Doing: Implement and own RTL for PCIe blocks and features from micro-architecture and design specs. Debug design issues in simulation and, as needed, in formal, emulation, or silicon bring-up support. Contribute to micro-architecture discussions for your blocks; document design intent and corner cases. Follow and help enforce RTL coding standards, lint/CDC hygiene, and review comments to closure. Work with verification to define coverage intent, root-cause failures, and deliver fixes on schedule. Support synthesis, timing, and low-power feedback from physical design for your blocks. Develop toward broader subsystem ownership with mentoring from Staff and Principal engineers. The Impact You Will Have: Deliver quality, maintainable RTL for silicon-proven PCIe IP. Improve execution speed and quality on assigned features Be part of Synopsys PCIe controller team delivering high-speed interface IP to leading customers. What You'll Need: BSEE with 5+ years of relevant experience, or MSEE with 3+ years (or equivalent). Hands-on ASIC RTL design in System Verilog on production designs. Experience with at least one of: PCIe, CXL, AMBA/AXI, DDR, Ethernet, or other high-speed / on-chip interconnect data paths. Working knowledge of clocking, resets, FSMs, pipelines, and synthesizable design practice. Familiarity with simulation debug; lint, CDC, or synthesis exposure is a plus. Scripting (Python, TCL, Perl) and AI-assisted design tools are a plus. Who You Are: A strong RTL engineer with quality mindeset who finishes what they own. Responsive in reviews and debug. Curious about protocol and micro-architecture At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email Linked In X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you