Staff Verification Applications Engineer at Synopsys

Learn more about applying for Staff Verification Applications Engineer at Synopsys requirements, reproduce issues, and influence the product roadmap based on real deployment feedback Lead competitive engagements by running benchmarks, demonstrating VCS/Verdi advantages, and helping customers evaluate simulation performance and debug efficiency Develop and optimize automation scripts in Perl, Tcl, Python, Shell, and Make to improve customer productivity and streamline verification workflows Interface directly with customers, product validation teams, and R&D to propose solutions, suggest product improvements, and close the loop on deployment challenges Support customers adopting AI-driven verification productivity tools and advanced simulation features as part of their methodology evolution The Impact You Will Have Enable customers to close verification faster and hit first-pass silicon by deploying simulation technology that actually scales to their design complexity Reduce time-to-tapeout for semiconductor companies building everything from mobile So Cs to automotive safety-critical designs Shape the VCS and Verdi product roadmap by surfacing real customer pain points and competitive gaps that R&D needs to address Drive adoption of advanced verification methodologies including UVM, Low Power, and Gate Level Timing simulation across global customer accounts Build long-term customer relationships that turn Synopsys tools into the backbone of their verification infrastructure Accelerate the industry's shift toward AI-augmented verification by helping customers integrate and adopt new productivity capabilities Strengthen Synopsys' competitive position in simulation and debug by winning benchmarks and proving performance in head-to-head evaluations What You'll Need Bachelor's or Master's degree in Electronics Engineering or related field with 5-12 years of hands-on experience in verification or applications engineering Strong working knowledge of VCS simulation technology and Verdi debug platform, or equivalent simulation and waveform debug tools Deep expertise in System Verilog, UVM, SVA, and verification methodologies applied to real RTL designs Proven experience with Low Power UPF flows and Gate Level Timing simulations in customer or product validation environments Advanced scripting ability in Perl, Tcl, Python, Shell, and Make for automation and flow development Solid understanding of digital design fundamentals, Verilog, VHDL, and UNIX/Linux environments Exposure to DPI, C/C++, System C, Functional Safety, or Gen AI technologies is a plus Who You Are You can explain a complex UVM sequence issue to a customer in two sentences and then write the 50-line reproducer that proves it Comfortable working across time zones with customers in Asia, Europe, and the US without losing momentum on open issues You manage multiple customer engagements at once, keeping track of what is blocking each one and what needs to escalate to R&D Self-directed enough to own a customer deployment from kickoff through production without waiting for someone to tell you what to do next You ask the questions that uncover the real problem, not just the symptoms the customer described in the ticket Open to travel for onsite customer engagements, competitive benchmarks, and team collaboration when it moves the work forward The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.