Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR

Learn more about applying for Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR at Synopsys Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 09/13/2026 Category Engineering Hire Type Employee Job ID 18582 Remote Eligible No Date Posted 09/13/2026 Alternate Job Titles Architect Digital Design -High Speed Memory Interface IP- HBM/DDR/LPDDR We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years building memory interface IP that has to work at the bleeding edge of performance, power, and reliability. Not just meet spec, but hold up under real-world corner cases that no one thought to write down. You know that the difference between a memory controller that ships and one that gets redesigned six months later is usually an architectural decision made early, and you are the kind of architect who sees around those corners. You think in tradeoffs. Bandwidth versus latency. Area versus configurability. What works in simulation versus what survives silicon. When someone asks if we can support a new HBM3 feature, you do not say yes or no, you say here is what it costs and here is what we get, and you have the depth to back it up with real numbers. You have worked across HBM, DDR, LPDDR, or similar high-speed memory protocols long enough to know where the complexity lives. Maybe it is training algorithms. Maybe it is clock domain crossings. Maybe it is how you partition the PHY interface so verification does not become a nightmare. You do not need to be told what matters, you already know. At Synopsys, you will define the architecture for memory IP that powers AI accelerators, data center processors, and mobile So Cs used by millions of people. The team is global, the problems are hard, and what you design will ship. What You'll Be Doing Define and own the digital architecture for HBM, DDR, or LPDDR memory controllers, from high-level partitioning through RTL implementation strategy Drive design plans for complex memory interface blocks, balancing performance, area, power, and verification complexity across chip and block levels Collaborate with PHY teams, verification engineers, and product architects to ensure seamless integration and protocol compliance Evaluate and select design methodologies, tools, and flows that improve quality, reduce cycle time, and scale across product lines Mentor engineers on architecture decisions, RTL best practices, and debug strategies for high-speed memory interfaces Work directly with customers and internal stakeholders to align on feature requirements, timing constraints, and delivery milestones Review and guide RTL, testbenches, and verification plans to catch architectural issues before they become silicon problems The Impact You Will Have Your architecture decisions will define the performance ceiling and power floor for memory IP used in next-generation AI and data center chips You will reduce time-to-market by building memory controllers that are easier to verify, integrate, and customize across multiple product variants The IP you help design will ship in millions of devices, from smartphones to high-performance computing systems You will elevate the technical depth of the team by mentoring engineers and establishing architectural patterns that scale Your ability to navigate ambiguity and make sound tradeoffs will directly influence which features ship and which get deferred You will help Synopsys maintain its leadership position in memory IP by driving innovations in HBM3, DDR5, LPDDR5X, and beyond The methodologies and design frameworks you put in place will improve quality and productivity across future memory IP projects What You'll Need 12 - 15+ years of hands-on experience in ASIC digital design, with significant time spent on memory interfaces or high-speed IO protocols Deep technical knowledge of at least one of HBM, DDR, LPDDR, or similar memory protocols, including controller architecture, training, and PHY interface Proven ability to define and execute complex digital architectures from concept through RTL implementation and silicon bring-up Strong understanding of AMBA or similar on-chip interconnect protocols and how memory controllers integrate into So C architectures Experience with advanced digital design tools and methodologies, including synthesis, timing closure, and low-power design techniques Excellent communication skills, you can explain a complex architectural tradeoff to a product manager, a verification lead, and a customer engineer without losing clarity Experience with HBM3, DDR5, or LPDDR5X is a strong plus Who You Are You can walk into a whiteboard session with incomplete requirements and walk out with a block diagram that the team can build from When an RTL review surfaces a potential issue, you do not defend the design, you ask the right questions and figure out if it is real You have a point of view on what good architecture looks like, and you are comfortable pushing back when a feature request does not make sense You think about verification complexity while you are designing, not after the RTL is done You are comfortable working across time zones with teams in the US, Europe, and Asia, and you know how to keep a distributed team aligned You do not need to be the one writing every line of RTL, but you can drop into the code and debug a corner case when it matters The Team You'll Be Part Of You will join a dynamic and focused team advancing Synopsys' memory interface IP portfolio. The team works on HBM, DDR, and LPDDR digital core protocols, collaborating closely with PHY, verification, and product teams across global sites. You will be a key technical contributor to the architecture and execution of one of these memory protocols, helping define what the next generation of memory IP looks like. The team values technical depth, clear communication, and the ability to solve hard problems without perfect information. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email Linked In X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you