ASIC Digital Design, Principal Engineer

Learn more about applying for ASIC Digital Design, Principal Engineer at Synopsys Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Date posted 09/13/2026 Category Engineering Hire Type Employee Job ID 18566 Remote Eligible No Date Posted 09/13/2026 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence—from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help transform the future through continuous technological innovation. You Are: You are a Principal ASIC Digital Design Engineer and a recognized PCIe technical authority. You set architecture and write and review RTL. You define micro-architecture, make trade-offs across performance, power, area, and configurability, and stay in the design until the IP is silicon-proven. You have shipped complex, highly parameterized high-speed interface IP. You are fluent in PCIe (Gen5/Gen6/Gen7) digital design—transaction layer, data path, link/controller functions, RAS, and power management—and you have working knowledge of adjacent protocols such as CXL, AMBA, DDR, or UCIe. You lead through architecture, design reviews, and direct technical engagement. You mentor senior and staff engineers, resolve complex issues, and represent the design in reviews with verification, physical design, customers, and senior management. What You'll Be Doing: Own PCIe digital architecture and RTL for major controller subsystems, from micro-architecture through design convergence and post-silicon support. Define micro-architecture, design specifications, and implementation approach for high-performance, low-power, scalable, configurable PCIe IP. Make and document key design decisions; act as the go-to authority for protocol, data-path, clocking/reset, and RAS issues. Hands-on RTL development: implement critical paths, review detailed design, and drive complex debug (simulation, formal, emulation, and silicon). Raise design quality bar through reviews, coding standards, CDC/RDC discipline, and RTL maintainability across a large parameterized codebase. Work with verification, formal, emulation, physical design, firmware, and system teams to get IP integrated and silicon-successful. Influence PCIe IP technical strategy, roadmap, and next-generation architecture, including CXL and automotive variants. Communicate status, technical risk, and trade-offs to senior management, architects, and customers. The Impact You Will Have: Deliver industry-leading PCIe digital IP used by leading commercial, enterprise, and automotive customers. Improve architectural quality, predictability, and execution on current and next-generation cores. Raise the technical bar across the design team through architecture leadership and mentorship. Strengthen Synopsys’ leadership position in high-speed interface IP. What You'll Need: BSEE with 12+ years of relevant experience, or MSEE with 10+ years. Demonstrated Principal / Staff-plus technical leadership in ASIC digital design Direct RTL ownership of complex, production digital designs Deep PCIe controller/core digital design and architecture experience, CXL, AMBA, DDR, UCIe, or similar protocols strongly desired. Proven ability to define micro-architecture and take designs from concept through silicon. Strong ASIC fundamentals: multi-clock design, CDC/RDC, resets, low power, DFT, synthesizable RTL, and timing-aware design. Experience with highly configurable / parameterized IP is strongly desired. Scripting for design automation (Python, TCL, Perl) is desirable. Familiarity with AI-assisted design tools and flows is a plus. Who You Are: A hands-on PCIe architect who leads by example in the RTL. Decisive on technical trade-offs; calm on the hardest debugs. A clear communicator across design, verification, PD, and customers. A mentor who multiplies the team and can create other technical leaders At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email Linked In X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You’ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you’re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you’ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you’ll be invited to join activities and training to help you ramp up for a successful future at Synopsys! BROWSE JOBS Find the open role that’s right for you