RTL Design Engineer

Tata Elxsi works with leading OEMs and suppliers in the automotive & transportation industries for R&D, Design and Product Engineering Services, right from architecture to launch and beyond. We bring together technologies that accelerate development & testing of connected autonomous and electric cars & off-highway vehicles. Key Responsibilities: Analyze specifications and develop micro-architecture for digital IPs and subsystems. Design and implement RTL using Verilog/ System Verilog. Perform RTL quality checks including linting, CDC/RDC analysis, and synthesis readiness. Support SoC/IP integration activities. Participate in design reviews and technical discussions. Collaborate with verification teams to resolve design issues and achieve quality sign-off.Support FPGA prototyping and silicon bring-up activities as required. Prepare and maintain design documentation. Required Skills: Strong proficiency in Verilog/SystemVerilog RTL coding. Good understanding of digital design fundamentals, FSMs, pipelining, clock-domain crossing, and timing concepts. Experience in ASIC/FPGA design and development flows. Knowledge of synthesis, timing analysis, lint, and CDC tools. Strong debugging and problem-solving skills.