Manager - Design Engineering

Tessolve · Remote

Source and collection record

Last observed by our collector: 9 October 2026 at 12:25 am IST. This is not a manual review or a confirmation from the employer.

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Collected role description

🔹 Key Responsibilities: • Design and develop synthesizable RTL using Verilog/System Verilog • Translate architecture specifications into micro-architecture and RTL implementation • Develop high-performance and low-power digital design blocks • Work closely with verification teams for functional validation and debug • Perform design reviews and ensure coding quality and design guidelines • Collaborate with physical design teams to meet timing, power, and area requirements • Debug RTL issues and support silicon bring-up when required 🔹 Required Skills: • Strong expertise in Verilog and System Verilog • Solid understanding of digital design fundamentals and computer architecture • Experience with AMBA protocols such as AXI, AHB, and APB • Knowledge of synthesis, timing closure, and low-power design techniques • Familiarity with simulation and debugging tools • Experience working in ASIC/SoC design environments 🔹 Preferred Qualifications: • Strong debugging and problem-solving skills • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. • Strong understanding of digital logic design principles.<br style="color:rgba(0,0,0,0.9);font-family:'system-ui', '-apple-system', BlinkMacSystemFont, 'Segoe UI', Roboto, Ubuntu, Oxygen, Cantarell, 'Fira Sans', 'Droid Sans', 'Helvetica Neue', Arial, sans-serif, 'Apple Color Emoji', 'Segoe UI Emoji', 'Segoe UI Symbol';white-space:pre-wrap;" />

Collected experience requirement

14 - 16 Years