Physical Design - Design Lead

<div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">About Us:</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve’s design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve’s Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Tessolve’s clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. </span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">For more details, visit https://www.tessolve.com/ </span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><b>Job Overview</b></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Join our team as a leader in physical design, spearheading the development of advanced SoC/ASIC projects. Your leadership will drive essential design processes, enhance collaboration across various engineering teams, and ensure top-notch design quality. Make a significant impact by mentoring engineers and implementing best practices that push the boundaries of innovation. This role is critical in delivering cutting-edge technology within the semiconductor industry.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Job Designation: Physical Design Team Lead / Sr. Design Engineer </span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Job Location: Bangalore</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><b>What you'll do</b></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Lead the physical design for SoC/ASIC projects.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Drive floorplanning, placement, and timing closure.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Collaborate with engineering teams for design quality.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Perform power analysis and integrity checks.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Manage sign-off activities for design verification.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><b>Who you are</b></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Skilled in SoC/ASIC design processes.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Proficient in power analysis and IR drop checks.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Collaborative and effective communicator.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Dedicated mentor for team development.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">· Committed to innovation and best practices.</span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;"><br /></span></font></div><div><font face="Calibri, sans-serif"><span style="font-size:14.6667px;">Tessolve Semiconductor Private Limited, as well as its affiliates and subsidiaries (“Tessolve”) does not require job applicants to make any payments at any stage of the hiring process. Any request for payment in exchange for a job opportunity at Tessolve is fraudulent and should be ignored. If you receive any such communication, we strongly advise you to refrain from making any payments and to promptly report the incident to us at hr@tessolve.com. Tessolve is not responsible for any losses incurred due to such fraudulent activities</span></font></div>