Design Verification Lead

Texas Instruments · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:25 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 25011177

Job type and experience labels are automated discovery categories. The employer determines eligibility. Retained employer experience wording: 5 years.

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Retained employer experience wording: 5 yearsAttendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

Change the world. Love your job. About the Team: The High-speed Data development team is focused on building state-of-the-art signal conditioning transceivers for Automotive, Industrial, Enterprise and Personal Electronics markets ranging from Ethernet PHY(s), FPD-Link Serdes & USB re-timers. The data rates range from 100Mbps to 40Gbps posing design challenges in high-speed circuit design and digital signal processing to enable data transfer with high fidelity in challenging industrial and automotive environments. These devices need to be competitive in power & area and are being designed in the 65nm and 28nm process nodes. The FPD product group charter is to develop High-speed Ser Des transceivers for Automotive targeting ADAS (Advanced driver-assistance systems) and In-Vehicle-Infotainment applications. These require high-reliability communication links that support auto-driving, and high-resolution graphic applications. The high-speed Ser Des designs require significant signal conditioning in Analog with Digital assist to calibrate / adapt the system in challenging electrical environments in the vehicle. The signal chain includes high bandwidth blocks (multi-Ghz) and signal processing data path designs that support multi-Gsps throughput involving clock recovery, channel adaptation, echo cancellation and forward error correction (FEC) to enable highly reliable links. Designed in 28nm CMOS process, the target for these designs is low power and low cost with best-in-industry performance. Minimum Requirements B.E/B.Tech or higher Digital design and modeling knowledge. Strong Debug skills 5 years of experience Preferred qualification: Design knowledge Soft Skills: Passion, Self-drive, Hard work, Willingness to learn Bachelor's Degree

Collected experience requirement

5 years