Design Verification Engineer

Texas Instruments · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:25 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 25010087

Job type and experience labels are automated discovery categories. The employer determines eligibility. Retained employer experience wording: 10 years.

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Retained employer experience wording: 10 yearsAttendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

About Group: Part of the ATD – Advanced Technology Group group of TI. We are a Team working on High-Density Flash Memory. The flash memory is used in various Connectivity, Industrial, Automotive and Application specific control applications . You will be a part of Flash Controller IP Design Verification Team , working on verification of the flash memory controller . What will you be doing in this role? (Responsibilities) Own part of IP DV from verification strategy to sign-off Coverage strategy & coverage closure (Functional, Code & Assertion coverage) Develop Test plans, verification strategy, test cases Use the right Verification strategy: Simulation, Formal, etc. Develop UVM components like agents, drivers, monitors and scoreboards Write assertion checks for DUT Use Formal apps like Connectivity, COV, UNR, FPV, etc. Debug the failures & report RTL bugs/Fix testbench Own the regressions for IP Improve the existing flows using latest methodologies/technologies Bachelors/Masters in VLSI or related field 5-10 yrs. Of Digital Design Verification Strong command in System Verilog & UVM Creating DV environment or tests for IP-level digital DV/So C level Developing DV testbenches, tests, assertion checking for DUT Experience in Verification tools like: Xcelium, Jasper Gold or similar Experience in Function & Code analysis & Closure Excellent debugging skills RTL Coding experience is a plus Experience in embedded memory verification is a plus Mixed digital/analog simulation (Verilog, AMS) is a plus Formal Verification experience is a plus Should be able to work with US Team What do we expect from you? (Mini Qualifications) Bachelors/Masters in VLSI or related field 5-10 yrs. Of Digital Design Verification Strong command in System Verilog & UVM Creating DV environment or tests for IP-level digital DV/So C level Developing DV testbenches, tests, assertion checking for DUT Experience in Verification tools like: Xcelium, Jasper Gold or similar Experience in Function & Code analysis & Closure Excellent debugging skills RTL Coding experience is a plus Experience in embedded memory verification is a plus Mixed digital/analog simulation (Verilog, AMS) is a plus Formal Verification experience is a plus Should be able to work with US Team Bachelor's Degree

Collected experience requirement

10 years