Memory Layout Design Engineer
UAW Technologies India Private Limited (UANDWE) · Bangalore
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Collected role description
Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology. Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. Skills: Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. We are looking for expertise on (Above 1 year): Understanding of memory architecture Experience in creating basic memory layouts from scratch Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers Knowledge of compiler issues Understanding of reliability issues Simulation effects EMI (Electromagnetic Interference) considerations
Collected minimum qualification
Bachelor's degree or higher in Computer Science or a related field.
Collected experience requirement
3 - 10 years of experience.