Design Verification (DV) Engineer – Mixed-Signal SoC

Experience: 5–12 years Skyworks is seeking a Design Verification Engineer to ensure functional correctness and robustness of mixed-signal SoC subsystems, including peripheral interfaces, audio blocks, and power management logic. You will work closely with RTL, architecture, and system teams to build comprehensive verification environments, drive coverage, and ensure first-pass silicon success. Key Responsibilities Verification Architecture & Planning Define and execute verification strategy for subsystems: SPI, UART, I2C, Audio interfaces (I2S, TDM), Power management digital controllers Develop test plans with full functional and corner-case coverage Identify verification risks and coverage gaps early UVM-Based Verification Development Build and maintain UVM/System Verilog testbenches Develop reusable VIPs and monitors, scoreboards and checkers, constrained-random stimulus Implement protocol-aware verification components Coverage & Quality Drive: functional coverage, code coverage (line, toggle, FSM) Ensure closure of coverage goals and assertion checks Track and report verification metrics Debug & Validation Debug RTL issues and root-cause failures Work closely with RTL engineers on bug fixes and improvements Support post-silicon validation with test reuse where applicable System-Level Verification Contribute to SoC-level verification: subsystem integration scenarios, firmware-driven tests Validate interactions across clock, reset, and power domains 5–12 years of DV experience in SoC/subsystem verification Strong expertise in System Verilog and UVM Functional coverage and assertions (SVA) Experience verifying AMBA protocols (AXI/AHB/APB) Experience verifying peripheral interfaces (SPI, UART, I2C, I2S/TDM preferred) Preferred Qualifications Experience with mixed-signal verification environments (AMS co-sim is a plus) Exposure to low-power verification (UPF/CPF) Familiarity with ARM Cortex-M33 or RISC-V SoCs