Principal Post-Silicon System Validation Engineer

onsemi India · Bangalore

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Last observed by our collector: 9 October 2026 at 12:41 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 2506724

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Collected minimum qualification: BS/MS/PhD in Electrical Engineering or related discipline.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

Principal Post-Silicon System Validation Engineer Position Summary The Principal Post-Silicon System Validation Engineer is responsible for defining and executing system-level validation strategies for Power Management Devices (PMD), ensuring robust product performance and quality from first silicon through production release. This individual contributor role requires deep expertise in semiconductor validation, power electronics, automation, characterization, and silicon debug. #LI-VS1 Key Responsibilities Develop and execute comprehensive validation plans covering functional, electrical, system, reliability, and application-level requirements. Lead silicon characterization, system validation, and root cause analysis of complex product and application issues. Design and implement automated validation solutions using LabVIEW, Python, NI PXI, and related platforms. Validate PMD products including SmartFETs, eFuses, power switches, gate drivers, and automotive power solutions. Collaborate with Design, Systems, Product Engineering, Applications, Quality, and Reliability teams to drive product readiness and issue resolution. Develop validation methodologies, best practices, and reusable automation frameworks. Influence future product designs through data-driven technical insights and validation expertise. #LI-VS1 Qualifications BS/MS/PhD in Electrical Engineering or related discipline. Grade 12: 5+ years of post-silicon validation, characterization, or systems engineering experience. Grade 13: 8+ years of experience with recognized technical leadership in validation and power management systems. Strong knowledge of analog/mixed-signal circuits, power electronics, automotive systems, and semiconductor validation methodologies. Expertise with laboratory instrumentation, automation, and debug techniques. Experience with LabVIEW, Python, and automated test systems. Preferred SmartFET, eFuse, Gate Driver, SBC, or automotive validation experience. Functional Safety, ISO 26262, ISO 21780, SiC/GaN, and AI-assisted validation experience. #LI-VS1

Collected minimum qualification

BS/MS/PhD in Electrical Engineering or related discipline.

Collected experience requirement

Grade 12: 5+ years of post-silicon validation, characterization, or systems engineering experience.