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Staff STA Engineer

onsemi India · Bangalore

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Employer requisition: 2506721

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Collected role description

Description OnSemi is seeking a Staff STA Engineer, NEW PRODUCT DEVELOPMENT, Power Management, to join our growing team in Bengaluru, India. This group is responsible for development of Power management products including DC-DC PMIC/POL, Multiphase controllers, Dr. MOS, AC-DC converters, LED drivers, SiC drivers, Switches and efuses for consumer, industrial and automotive applications. #LI-VS1 Responsibilities STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc…) Generating ECO for timing closure for complex multi power domain designs Good experience in running STA regression with high number of modes/corners efficiently. Power recovery with STA signoffDebug constraint issues in P&R environment LEC/Low power checks experience Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Strong in problem solving with deep understanding of technical issues. Candidate should have keen eye to improve existing flow and methods with positive impact on PPA. #LI-VS1 Qualifications BE in Electrical Engineering or related + 6 years of experience, or M.Tech + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF Solid understanding of Verilog, TCL and Perl/Python/XML programming languages Solid track record of releasing complex ICs to market Ability to clearly articulate issues, challenges, and concerns to all levels of management Must have good written and verbal cross-functional communication skills #LI-VS1

Collected minimum qualification

Solid understanding of RTL design, CDC, ASIC synthesis, timing analysis and CDC, P&R, UPF

Collected experience requirement

BE in Electrical Engineering or related + 6 years of experience, or M.Tech + 5 years of experience in working and leading Digital Design, Architecture and ASIC/Mixed signal chip developments