Staff Engineer - DV

Job Description: RESPONSIBILITIES: Hands on system Verilog/UVM development work for modern high performance CPU verification. Work will involve writing test cases, using test generators to generate targeted tests for RISCV CPU verification. Working with internal test generators to target coverage/test-plan scenarios. Requirements: 7-12 years of experience in DV preferably in CPU verification with a Bachelor's or Master's in Engineering Proficiency in System Verilog and UVM methodology. Very good object-oriented programming skills. Any CPU architecture knowledge (x86, ARM or RISC-V) with test writing/test plan implementation experience. Any scripting knowledge, preferably python. Bus interface knowledge like AXI or PCIE Integration experience with third party VIPs like bus VIPs. Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. Si Five is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. Championed by leaders who chose to make a real difference, Si Five led the RISC-V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we’ve made history, you have the opportunity to write the future. If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.