Staff Design Verification Infrastructure Engineer - VIPs and Testbench
SiFive · Bangalore
Source and collection record
Last observed by our collector: . This is not a manual review or a confirmation from the employer.
Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.
Your application evidence checklist
Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.
0 of 2 checks marked. Keep unresolved requirements as questions for the employer.
Collected role description
Job Description: Join Si Five’s Design Verification Infrastructure team to develop and maintain the Verification Platform VIPs, AIPs, and other testbench components used across Si Five. An ideal candidate will be a strong Design Verification engineer with a solid understanding of software engineering. You will be expected to collaborate with Design Verification engineers to develop reusable testbench components and integrate them within Si Five’s Chisel-based Verification Platform.. RESPONSIBILITIES: Architect, develop, and maintain the Verification Platform to provide a common infrastructure that scales with the growth of Si Five for Design Verification and other verification and validation activities Develop Verification Platform libraries for expressing verification intent in Scala with Chisel, including test harnesses, stimulus, scoreboards, and other generators Develop Verification Platform VIPs, AIPs, and other testbench components using System Verilog, UVM, and other related technologies Develop Verification Platform test plans and testbenches to verify and release testbench components with high quality Educate the Design Verification and other verification and validation teams on best practices and how to achieve them with the Verification Platform Requirements: Design Verification experience with System Verilog and UVM Experience designing and verifying VIPs, AIPs, and other testbench components Understanding of modern software engineering practices Desired: Experience with Chisel, Scala, and/or Python Understanding of EDA tools and flows for Design Verification Familiarity with Dev Ops practices, build systems, and CI / CD Additional Information: This position requires a successful background and reference checks and satisfactory proof of your right to work in: India Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals. Si Five is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. Championed by leaders who chose to make a real difference, Si Five led the RISC-V revolution—creating a tremendous wave with the strength to remove economic hurdles and create opportunities for all. Now that we’ve made history, you have the opportunity to write the future. If you love to be challenged, you can join the best of the best and get rewarded for doing something that truly matters.