STA Engineer - EDA/CAD Flow : Software Development Engineer

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 93342

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. STA Engineer - EDA/CAD Flow : Software Development Engineer THE ROLE: <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"37480bbf-7d84-44c2-b9d6-8ffae6858199|84","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">We are looking for a dynamic, upbeat software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"37480bbf-7d84-44c2-b9d6-8ffae6858199|85","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> THE PERSON: The ideal candidate should have a strong background in RTL design using Verilog/VHDL and strong exposure to timing closure concepts with foundations in timing analysis & digital design. KEY RESPONSIBILITIES: The candidate should have a solid understanding of <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">RTL coding styles</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">STA and Timing Constraint Concepts</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Place and route algoritms and applications. </li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">The candidate will be responsible for creating complex designs, debugging P & R issues and will work to achieve timing closure.</li></ul> PREFERRED EXPERIENCE: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Scripting language such as TCL, Perl or Python</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">EDA tools and flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with Linux and modern software tools and techniques for development</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good analytical and problem-solving skills </li></ul> ACADEMIC CREDENTIALS: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">BS or MS in EE or CE with 2-3 years of experience in Digital Design and Static Timing Analysis</li></ul> #LI-SG2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

STA Engineer - EDA/CAD Flow : Software Development Engineer THE ROLE: <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"37480bbf-7d84-44c2-b9d6-8ffae6858199|84","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">We are looking for a dynamic, upbeat software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"37480bbf-7d84-44c2-b9d6-8ffae6858199|85","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}">   THE PERSON: The ideal candidate should have a strong background in RTL design using Verilog/VHDL and strong exposure to timing closure concepts with foundations in timing analysis & digital design.  KEY RESPONSIBILITIES: The candidate should have a solid understanding of <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">RTL coding styles</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">STA and Timing Constraint Concepts</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Place and route algoritms and applications. </li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">The candidate will be responsible for creating complex designs, debugging  P & R issues and will work to achieve timing closure.</li></ul> PREFERRED EXPERIENCE: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Scripting language such as TCL, Perl or Python</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">EDA tools and flow</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with Linux and modern software tools and techniques for development</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good analytical and problem-solving skills </li></ul> ACADEMIC CREDENTIALS: <ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">BS or MS in EE or CE with 2-3  years of experience in Digital Design and Static Timing Analysis</li></ul> #LI-SG2

Collected experience requirement

2-3 years