Lead DFT Engineer

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 92788

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">LEAD DFT ENGINEER <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Implementation and verification of DFT features like SCAN, MBIST, LBIST and JTAG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Support Spyglass-DFTDRC debug and coverage correlation</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Scan insertion and ATPG pattern generation </li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">ATPG patterns verification with gate-level simulation </li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Test coverage and test cost reduction analysis </li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: #32363a; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Post silicon support to ensure successful bring up and enhance yield learning</li></ul> PREFERRED EXPERIENCE: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in scan-stitching; and has good knowledge of scan-stitching related concepts</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on ATPG; and is well conversed with the files required to run ATPG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge/experience with Tessent ATPG (mentor) is a plus</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on Spyglass-DFT</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on debug skills and scripting skills are critical</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on automation scripts like TCL/AWK/SED is a plus</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understands the basics of JTAG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon bring up is a plus</li></ul> ACADEMIC CREDENTIALS: Bachelors degree with 7+ years or Masters degree with 5+ years in Electronics engineering/Electrical Engineering #LI-NS1 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">LEAD DFT ENGINEER <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: We are looking for an adaptive, self-motivative DFT engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The DFT team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.  THE PERSON: You have a passion for modern, digital design, and DFT in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  KEY RESPONSIBILITIES: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Implementation and verification of DFT features like SCAN, MBIST, LBIST and JTAG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Support Spyglass-DFTDRC debug and coverage correlation</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Scan insertion and ATPG pattern generation </li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">ATPG patterns verification with gate-level simulation </li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Test coverage and test cost reduction analysis </li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; color: #32363a; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Post silicon support to ensure successful bring up and enhance yield learning</li></ul> PREFERRED EXPERIENCE: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in scan-stitching; and has good knowledge of scan-stitching related concepts</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to MBIST/BISR implementation and with the Tessent flow of mbist-insertion</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on ATPG; and is well conversed with the files required to run ATPG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge/experience with Tessent ATPG (mentor) is a plus</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on Spyglass-DFT</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent hands-on debug skills and scripting skills are critical</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge on automation scripts like TCL/AWK/SED is a plus</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understands the basics of JTAG</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon bring up is a plus</li></ul> ACADEMIC CREDENTIALS: Bachelors degree with 7+ years or Masters degree with 5+ years in Electronics engineering/Electrical Engineering #LI-NS1

Collected experience requirement

7+ years