Server platform design architect

AMD · Bangalore

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 92579

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. <div class="row-start-1 col-start-1 min-w-0"><div class="min-w-0 pl-[var(--msg-text-inset,0.5rem)] py-[var(--msg-pill-py,0.375rem)]"><div class="flex items-center gap-2"><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">Server platform design architect</h1><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;"> </h1><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">THE ROLE:</h1> Function: Principal Member of Technical Staff | Discipline: High Speed Board Design & Server Platform Architecture | Level: Principal / Staff (Senior Individual Contributor) | Location: Bangalore, India | Department: Server Platform Design / System Hardware Engineering We are looking for an exceptionally skilled and experienced Principal Member of Technical Staff to join our Server platform Hardware Engineering team, specializing in High Speed Board Design. This is a senior individual contributor role that combines deep technical expertise with leadership responsibility across complex, multi-generational hardware programs. The ideal candidate is a seasoned hardware engineer who thrives at the intersection of signal integrity, power integrity, and system-level design — someone who can independently drive technically complex designs from concept to production while also guiding and mentoring the engineers around them. This role operates at the forefront of hardware innovation, working on high-performance computing platforms, data center solutions, or next-generation semiconductor evaluation and validation systems. The engineer in this role will be expected to define technical direction, establish design methodology, and be the go-to authority for high speed board design challenges across the organization. <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">THE PERSON:</h1> The ideal candidate brings a rare combination of deep hardware expertise and collaborative leadership. They are recognised as the go-to authority in platform design — someone who can resolve complex problems that others cannot, while remaining humble enough to mentor and grow the engineers around them. They demonstrate full ownership — from concept to production — and approach ambiguous, multi-disciplinary problems with a systematic mindset. They communicate complex technical concepts clearly to both technical and non-technical audiences, and represent the team with confidence in cross-functional and vendor discussions. Above all, they have an innovation mindset — constantly looking for better ways to design, review, and validate hardware — and they actively invest in the growth of the engineers around them. They are collaborative across disciplines (SI, firmware, mechanical, test, silicon) and comfortable navigating shifting priorities and new technology domains. What success looks like:In the first 6 months: Deep understanding of team programs, tools, and design standards; actively contributing to design reviews and board bring-up; identified at least one methodology improvement opportunity.Within the first year: Owning one or more high-speed board designs from specification through layout sign-off; recognised as a trusted technical resource; contributed to or defined updated design standards.Over time: Defining the technical direction for platform architecture within the organisation; producing benchmark designs for quality and reliability; developing the next generation of hardware design engineers on the team. <h1 style="margin: 0.05pt 0in 0in; font-size: 12pt; font-family: Arial, sans-serif;">KEY RESPONSIBILITIES:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Technical Design & Execution</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Lead the end-to-end design of high-speed, high-complexity PCBs including schematic capture, component selection, layout guidance, and design verification</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Design and review high-speed interfaces including PCIe Gen 4/5/6, DDR4/5/LPDDR5, USB 3.x, MIPI, SERDES-based interfaces, Ethernet (1G/10G/25G/100G), and other emerging standards</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Develop and own design specifications, interface requirement documents, and schematics for complex multi-layer boards (20+ layers)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define and enforce PCB stack-up, impedance control, and routing rules for high-speed signal integrity compliance</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Drive board bring-up, debug, and validation activities — capable of independently diagnosing and resolving complex hardware issues</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Perform or guide pre-layout and post-layout signal integrity (SI) and power integrity (PI) simulations using industry-standard tools</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Work closely with PCB layout engineers to ensure design intent is correctly implemented, performing detailed layout reviews and providing clear, specific guidance</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Architecture & Innovation</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Participate in early-stage architecture definition and feasibility assessment for new platform programs</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Evaluate new silicon devices, connectors, memory technologies, and interface standards and assess applicability to upcoming designs</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define reference design guidelines and best practices for high speed board design within the team</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Identify and propose design improvements that reduce cost, improve reliability, extend product life, or enhance testability</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Stay current with industry trends, emerging standards, and evolving EDA tool capabilities</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Technical Leadership & Mentorship</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Serve as the technical authority and subject matter expert (SME) for high speed board design within the team</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Provide technical guidance, design reviews, and mentorship to junior and mid-level hardware engineers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Lead design reviews — both internal and cross-functional — ensuring design quality, manufacturability, and compliance with system requirements</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Collaborate with cross-functional teams including signal integrity engineers, firmware engineers, mechanical designers, and test engineers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Represent the hardware design team in technical discussions with silicon vendors, EDA tool vendors, PCB fabricators, and assembly partners</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Process & Quality</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define and maintain design standards, checklists, and review processes for high speed board design</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Champion design for manufacturability (DFM), design for testability (DFT), and design for reliability (DFR) practices</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Drive continuous improvement in design methodology, tool flows, and review processes</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Support sustaining engineering activities including ECO management, alternate component qualification, and product improvements</li></ul> <h1 style="margin: 13.8pt 0in 0in; font-size: 12pt; font-family: Arial, sans-serif;">PREFERRED EXPERIENCE:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">REQUIRED TECHNICAL SKILLS</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Deep expertise in high-speed interface design: PCIe (Gen 4/5 minimum), DDR4/DDR5, USB 3.x, SERDES-based interfaces</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Strong hands-on experience with signal integrity analysis — pre/post layout simulation, eye diagram analysis, impedance modeling, crosstalk analysis</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Strong hands-on experience with power integrity analysis — PDN design, decoupling strategy, VRM placement, DC/AC analysis</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Proficiency in schematic capture tools — Cadence Allegro/OrCAD, Mentor PADS, or equivalent industry tools</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Practical experience guiding PCB layout engineers — routing rules, layer stack-up, via structures, differential pair routing, length matching, and return path management</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with board bring-up and hardware debug — oscilloscope, logic analyzer, VNA, TDR, BERT, and protocol analyzers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Familiarity with EMI/EMC design practices and compliance requirements (FCC, CE, etc.)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Understanding of thermal design considerations for high-power components</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Knowledge of manufacturing processes — DFM, IPC standards, Gerber review, assembly and test</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">PREFERRED / BONUS SKILLS</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with FPGA-based boards (Xilinx/AMD or Intel FPGA integration)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Exposure to high-speed optical or SerDes interfaces at 112G or beyond</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with OCP/DC-SCM, OpenBMC, IPMI, or data center platform standards</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Familiarity with RTL or firmware development for hardware validation or embedded systems</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with mechanical design tools (ECAD-MCAD co-design)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Exposure to AI/ML-based EDA tools or automation of design review and verification processes</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience in JTAG infrastructure design and boundary scan methodology</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">EXPERIENCE</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">15+ years of hands-on experience in PCB hardware design, with a strong focus on high-speed digital systems</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Demonstrated experience designing complex, multi-layer PCBs (16+ layers) for high-performance computing, server, networking, or semiconductor test and evaluation platforms</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Proven track record of successfully delivering hardware designs from concept through mass production or customer deployment</li></ul> <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">ACADEMIC CREDENTIALS:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a closely related field (preferred)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Master's degree in Electrical Engineering or related discipline (preferred / desired)</li></ul> <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">LOCATION:</h1><ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Bangalore, India</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Department: Server Platform Design / System Hardware Engineering</li></ul> #LI-SK3</div></div></div> Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<div class="row-start-1 col-start-1 min-w-0"><div class="min-w-0 pl-[var(--msg-text-inset,0.5rem)] py-[var(--msg-pill-py,0.375rem)]"><div class="flex items-center gap-2"><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">Server platform design architect</h1><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;"> </h1><h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">THE ROLE:</h1> Function: Principal Member of Technical Staff  |  Discipline: High Speed Board Design & Server Platform Architecture  |  Level: Principal / Staff (Senior Individual Contributor)  |  Location: Bangalore, India  |  Department: Server Platform Design / System Hardware Engineering We are looking for an exceptionally skilled and experienced Principal Member of Technical Staff to join our Server platform Hardware Engineering team, specializing in High Speed Board Design. This is a senior individual contributor role that combines deep technical expertise with leadership responsibility across complex, multi-generational hardware programs. The ideal candidate is a seasoned hardware engineer who thrives at the intersection of signal integrity, power integrity, and system-level design — someone who can independently drive technically complex designs from concept to production while also guiding and mentoring the engineers around them. This role operates at the forefront of hardware innovation, working on high-performance computing platforms, data center solutions, or next-generation semiconductor evaluation and validation systems. The engineer in this role will be expected to define technical direction, establish design methodology, and be the go-to authority for high speed board design challenges across the organization. <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">THE PERSON:</h1> The ideal candidate brings a rare combination of deep hardware expertise and collaborative leadership. They are recognised as the go-to authority in platform design — someone who can resolve complex problems that others cannot, while remaining humble enough to mentor and grow the engineers around them. They demonstrate full ownership — from concept to production — and approach ambiguous, multi-disciplinary problems with a systematic mindset. They communicate complex technical concepts clearly to both technical and non-technical audiences, and represent the team with confidence in cross-functional and vendor discussions. Above all, they have an innovation mindset — constantly looking for better ways to design, review, and validate hardware — and they actively invest in the growth of the engineers around them. They are collaborative across disciplines (SI, firmware, mechanical, test, silicon) and comfortable navigating shifting priorities and new technology domains. What success looks like:In the first 6 months: Deep understanding of team programs, tools, and design standards; actively contributing to design reviews and board bring-up; identified at least one methodology improvement opportunity.Within the first year: Owning one or more high-speed board designs from specification through layout sign-off; recognised as a trusted technical resource; contributed to or defined updated design standards.Over time: Defining the technical direction for platform architecture within the organisation; producing benchmark designs for quality and reliability; developing the next generation of hardware design engineers on the team. <h1 style="margin: 0.05pt 0in 0in; font-size: 12pt; font-family: Arial, sans-serif;">KEY RESPONSIBILITIES:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Technical Design & Execution</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Lead the end-to-end design of high-speed, high-complexity PCBs including schematic capture, component selection, layout guidance, and design verification</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Design and review high-speed interfaces including PCIe Gen 4/5/6, DDR4/5/LPDDR5, USB 3.x, MIPI, SERDES-based interfaces, Ethernet (1G/10G/25G/100G), and other emerging standards</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Develop and own design specifications, interface requirement documents, and schematics for complex multi-layer boards (20+ layers)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define and enforce PCB stack-up, impedance control, and routing rules for high-speed signal integrity compliance</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Drive board bring-up, debug, and validation activities — capable of independently diagnosing and resolving complex hardware issues</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Perform or guide pre-layout and post-layout signal integrity (SI) and power integrity (PI) simulations using industry-standard tools</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Work closely with PCB layout engineers to ensure design intent is correctly implemented, performing detailed layout reviews and providing clear, specific guidance</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Architecture & Innovation</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Participate in early-stage architecture definition and feasibility assessment for new platform programs</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Evaluate new silicon devices, connectors, memory technologies, and interface standards and assess applicability to upcoming designs</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define reference design guidelines and best practices for high speed board design within the team</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Identify and propose design improvements that reduce cost, improve reliability, extend product life, or enhance testability</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Stay current with industry trends, emerging standards, and evolving EDA tool capabilities</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Technical Leadership & Mentorship</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Serve as the technical authority and subject matter expert (SME) for high speed board design within the team</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Provide technical guidance, design reviews, and mentorship to junior and mid-level hardware engineers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Lead design reviews — both internal and cross-functional — ensuring design quality, manufacturability, and compliance with system requirements</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Collaborate with cross-functional teams including signal integrity engineers, firmware engineers, mechanical designers, and test engineers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Represent the hardware design team in technical discussions with silicon vendors, EDA tool vendors, PCB fabricators, and assembly partners</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Process & Quality</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Define and maintain design standards, checklists, and review processes for high speed board design</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Champion design for manufacturability (DFM), design for testability (DFT), and design for reliability (DFR) practices</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Drive continuous improvement in design methodology, tool flows, and review processes</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Support sustaining engineering activities including ECO management, alternate component qualification, and product improvements</li></ul> <h1 style="margin: 13.8pt 0in 0in; font-size: 12pt; font-family: Arial, sans-serif;">PREFERRED EXPERIENCE:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">REQUIRED TECHNICAL SKILLS</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Deep expertise in high-speed interface design: PCIe (Gen 4/5 minimum), DDR4/DDR5, USB 3.x, SERDES-based interfaces</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Strong hands-on experience with signal integrity analysis — pre/post layout simulation, eye diagram analysis, impedance modeling, crosstalk analysis</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Strong hands-on experience with power integrity analysis — PDN design, decoupling strategy, VRM placement, DC/AC analysis</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Proficiency in schematic capture tools — Cadence Allegro/OrCAD, Mentor PADS, or equivalent industry tools</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Practical experience guiding PCB layout engineers — routing rules, layer stack-up, via structures, differential pair routing, length matching, and return path management</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with board bring-up and hardware debug — oscilloscope, logic analyzer, VNA, TDR, BERT, and protocol analyzers</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Familiarity with EMI/EMC design practices and compliance requirements (FCC, CE, etc.)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Understanding of thermal design considerations for high-power components</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Knowledge of manufacturing processes — DFM, IPC standards, Gerber review, assembly and test</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">PREFERRED / BONUS SKILLS</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with FPGA-based boards (Xilinx/AMD or Intel FPGA integration)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Exposure to high-speed optical or SerDes interfaces at 112G or beyond</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with OCP/DC-SCM, OpenBMC, IPMI, or data center platform standards</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Familiarity with RTL or firmware development for hardware validation or embedded systems</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience with mechanical design tools (ECAD-MCAD co-design)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Exposure to AI/ML-based EDA tools or automation of design review and verification processes</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Experience in JTAG infrastructure design and boundary scan methodology</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">EXPERIENCE</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">15+ years of hands-on experience in PCB hardware design, with a strong focus on high-speed digital systems</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Demonstrated experience designing complex, multi-layer PCBs (16+ layers) for high-performance computing, server, networking, or semiconductor test and evaluation platforms</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Proven track record of successfully delivering hardware designs from concept through mass production or customer deployment</li></ul> <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">ACADEMIC CREDENTIALS:</h1> <ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Bachelor's degree or higher in Electrical Engineering, Electronics Engineering, or a closely related field (preferred)</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Master's degree in Electrical Engineering or related discipline (preferred / desired)</li></ul> <h1 style="margin: 0in; font-size: 12pt; font-family: Arial, sans-serif;">LOCATION:</h1><ul style="margin-bottom: 0in; margin-top: 0px;"><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Bangalore, India</li><li style="margin: 0in 0in 0in 0px; font-size: 11pt; font-family: Arial, sans-serif;">Department: Server Platform Design / System Hardware Engineering</li></ul> #LI-SK3</div></div></div>

Collected experience requirement

15+ years