Lead System Development Engineer

<strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;"><strong>ADVANCE YOUR CAREER. ADVANCE THE WORLD. </strong></span></p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. </span></p><p style="margin: 0px;"> </p><p style="margin: 0px;"><span style="font-size: 12pt; font-family: arial, helvetica, sans-serif;">Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead System Development Engineer </span></strong></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">THE ROLE:</span></strong></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">AMD is looking for a Lead System Development Engineer to join a team enabling AI inference on AMD's Versal AI Edge SoC platforms. You will work across the full vertical stack — collaborating with embedded Linux, AI runtime, hardware, and platform teams to integrate, validate, and deliver AI solutions on AMD's latest AI Edge hardware. The role spans System design, board bring-up, BSP integration, AI runtime enablement, System characterization, and application pipeline development, with a strong focus on system-level quality and customer readiness</span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">THE PERSON:</span></strong></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">The ideal candidate operates at the hardware-software boundary — someone who can design and implement FPGA/SoC subsystems, profile and characterize hardware designs, and debug issues that span RTL, firmware, and software layers. You are equally comfortable in a design tool analyzing timing or resource utilization as you are reading a device driver or inference runtime log. You take ownership of complex, cross-layer problems and drive them to resolution independently.</span></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">KEY RESPONSIBILITIES:</span></strong></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Design, implement, and verify FPGA/SoC subsystems for AI edge platforms, including hardware accelerator integration, IP configuration, and design bring-up</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Profile and characterize hardware designs — timing closure, resource utilization, power analysis, and thermal behavior — and drive identified issues to resolution</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Debug design-specific hardware issues using in-system debug tools (logic analyzers, hardware monitors, JTAG) and correlate findings across RTL, firmware, and software layers</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead platforms bring-up activities for new AI edge SoC hardware, including boot flow validation, storage subsystem integration, and peripheral initialization</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Integrate and validate AI inference runtimes and hardware accelerator stacks on embedded SoC targets, debug performance, correctness, and model deployment issues end-to-end</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Support deep learning model compilation, quantization, and optimization workflows targeting embedded AI accelerators (NPU/DPU/spatial compute engines)</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Develop and maintain Yocto-based embedded Linux — recipes, layers, rootfs configuration, and kernel/driver integration</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Write tooling and automation to support hardware validation, device programming workflows, and CI/CD pipelines</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Partner with hardware and silicon teams on system stability, power characterization, and platform validation</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Contribute to technical documentation, release notes, and customer-facing enablement content</span></li></ul></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> </span></strong></p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">PREFERRED EXPERIENCE:</span></strong></p><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Hands-on FPGA/SoC design experience: RTL integration, IP configuration</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Experience with FPGA design tools (Vivado or equivalent) for implementation, resource analysis, power estimation, and in-system debug</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Proficiency with hardware profiling and characterization: performance benchmarking, power/thermal analysis, and design-specific bottleneck identification</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Proficiency with low-level hardware debug tools: JTAG, in-system logic analyzers, hardware monitors, signal analyzers</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Strong C/C++ development skills with emphasis on embedded and systems-level code quality</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Experience with embedded NPU, DPU, or spatial/dataflow AI accelerators — integration, debugging, and performance tuning</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Hands-on experience deploying AI inference frameworks on edge or embedded hardware — ONNX Runtime, TensorFlow Lite, TensorRT, or equivalent vendor-specific runtimes</span></li></ul></ul><ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><ul style="margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Hands-on Yocto/Open Embedded and embedded Linux experience: BSP bring-up (bootloaders, device trees, kernel drivers), recipe authoring, layer customization, and rootfs configuration</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Working knowledge of hardware acceleration concepts: DMA, memory-mapped I/O, PCIe, interrupt handling, shared memory buffers</span></li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Experience with GStreamer or comparable multimedia/dataflow pipeline frameworks for hardware-accelerated workloads is a plus</span></li></ul></ul><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </p><p style="margin: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">#LI-PK1</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>