Physical Design Engineer

AMD · Bangalore

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 93022

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Physical Design Engineer :EMIR / PDN Domain: ASIC / SoC Physical Design, EMIR THE ROLE:We are looking for an adaptive, self-motivated Senior Silicon Design Engineer with strong experience in Electromigration and IR Drop (EMIR) analysis to join our growing team.As a key contributor, you will be responsible for driving EMIR analysis, debug, and signoff closure for complex, high-performance SoC designs using industry-standard tools such as Ansys RedHawk-SC and Cadence Voltus.You will collaborate closely with Physical Design, Power, Package, and other cross-functional teams to identify power integrity risks, perform root-cause analysis, recommend design improvements, and drive issues to closure.You will also contribute to improving EMIR methodologies, automation, flow efficiency, and overall design quality to enable robust and reliable silicon. THE PERSON: You have a passion for silicon design, physical design, and solving complex EMIR challenges. You possess a strong understanding of power delivery networks and the interaction between floorplan, power grid, placement, routing, bumps, power distribution, and design activity.You are a team player with excellent communication and collaboration skills and are comfortable working with engineers across different teams, sites, and time zones.You have strong analytical and problem-solving skills, with the ability to independently debug complex EMIR issues, identify root causes, propose practical design solutions, and drive issues to closure.You are self-motivated, willing to learn, and continuously look for opportunities to improve methodologies, automation, debug efficiency, and overall design convergence. KEY RESPONSIBILITIES:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform static and dynamic IR-drop and Electromigration analysis using industry-standard EMIR tools such as Ansys RedHawk-SC and Cadence Voltus for complex SoC designs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop, maintain, and validate EMIR flows and analysis setups across different stages of the physical design cycle.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform power-grid validation and identify weak-grid regions, voltage-drop hotspots, current-density violations, and power connectivity issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate EMIR database quality and input data integrity, and identify setup or data-related issues that could impact the accuracy and quality of EMIR analysis.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform detailed root-cause analysis of EMIR violations and provide actionable recommendations to Physical Design and other related teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work closely with Physical Design teams to drive power-grid optimization, via enhancement, metal strengthening, floorplan updates, placement optimization, and ECO-based fixes.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze EMIR challenges associated with voltage islands, multiple power domains, power-domain boundaries, bump distribution, and power-grid connectivity.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify critical issues early in the design cycle that may require floorplan, bump, or power-grid architecture changes.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze results across multiple design iterations to identify new violations, regressions, and unexpected changes, and drive them toward resolution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work closely with design teams to determine whether identified EMIR issues can be addressed through ECO changes or require more significant power-grid/design modifications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive assigned blocks/subsystems toward EMIR signoff and design convergence, while meeting project quality and schedule requirements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop and improve automation for EMIR flow execution, data processing, analysis, debug, and reporting.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate effectively with cross-functional teams and provide technical guidance and support on EMIR related issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Contribute to continuous improvement of EMIR methodologies, checks, best practices, and design closure processes.</li></ul>PREFERRED EXPERIENCE:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">4 +Years of hands-on experience in ASIC/SoC Physical Design with significant experience in EMIR analysis and signoff.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong hands-on experience with Ansys RedHawk-SC and/or Cadence Voltus for Electromigration and IR-drop analysis. Experience with both tools is highly preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of Power Delivery Networks (PDN), static IR drop, dynamic IR drop, Electromigration, current density, and power-grid reliability.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with EMIR flow setup, database validation, debug, analysis, and signoff closure.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of the impact of floorplan, placement, routing, power-grid design, vias, and bumps on EMIR.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in debugging EMIR violations and providing effective and practical design recommendations for issue resolution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of multi-voltage designs, voltage islands, and power-domain interactions.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in power-grid robustness analysis and validation and identifying potential design weaknesses early in the implementation cycle.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with physical design inputs and data such as LEF/DEF, parasitics, power/activity data, technology files, power intent, and design databases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of the overall ASIC Physical Design flow from floorplanning through implementation, ECO, and signoff.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with scripting languages such as Python, Tcl, Perl, and/or Shell for flow automation, data analysis, reporting, and productivity improvement.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience working on advanced-node, high-performance, or large-scale SoC designs is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with hierarchical/block-to-top EMIR analysis methodologies is an added advantage.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to chip/package power-integrity interactions, bump planning, and package-related power delivery considerations is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to independently analyze large amounts of EMIR data, identify trends and systematic issues, and drive corrective actions.</li></ul>ACADEMIC CREDENTIALS:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, VLSI, Microelectronics, or a related discipline.#LI-SR5</li></ul> Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

Physical Design Engineer :EMIR / PDN Domain: ASIC / SoC Physical Design, EMIR THE ROLE:We are looking for an adaptive, self-motivated Senior Silicon Design Engineer with strong experience in Electromigration and IR Drop (EMIR) analysis to join our growing team.As a key contributor, you will be responsible for driving EMIR analysis, debug, and signoff closure for complex, high-performance SoC designs using industry-standard tools such as Ansys RedHawk-SC and Cadence Voltus.You will collaborate closely with Physical Design, Power, Package, and other cross-functional teams to identify power integrity risks, perform root-cause analysis, recommend design improvements, and drive issues to closure.You will also contribute to improving EMIR methodologies, automation, flow efficiency, and overall design quality to enable robust and reliable silicon. THE PERSON: You have a passion for silicon design, physical design, and solving complex EMIR challenges. You possess a strong understanding of power delivery networks and the interaction between floorplan, power grid, placement, routing, bumps, power distribution, and design activity.You are a team player with excellent communication and collaboration skills and are comfortable working with engineers across different teams, sites, and time zones.You have strong analytical and problem-solving skills, with the ability to independently debug complex EMIR issues, identify root causes, propose practical design solutions, and drive issues to closure.You are self-motivated, willing to learn, and continuously look for opportunities to improve methodologies, automation, debug efficiency, and overall design convergence. KEY RESPONSIBILITIES:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform static and dynamic IR-drop and Electromigration analysis using industry-standard EMIR tools such as Ansys RedHawk-SC and Cadence Voltus for complex SoC designs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop, maintain, and validate EMIR flows and analysis setups across different stages of the physical design cycle.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform power-grid validation and identify weak-grid regions, voltage-drop hotspots, current-density violations, and power connectivity issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate EMIR database quality and input data integrity, and identify setup or data-related issues that could impact the accuracy and quality of EMIR analysis.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform detailed root-cause analysis of EMIR violations and provide actionable recommendations to Physical Design and other related teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work closely with Physical Design teams to drive power-grid optimization, via enhancement, metal strengthening, floorplan updates, placement optimization, and ECO-based fixes.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze EMIR challenges associated with voltage islands, multiple power domains, power-domain boundaries, bump distribution, and power-grid connectivity.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify critical issues early in the design cycle that may require floorplan, bump, or power-grid architecture changes.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze results across multiple design iterations to identify new violations, regressions, and unexpected changes, and drive them toward resolution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Work closely with design teams to determine whether identified EMIR issues can be addressed through ECO changes or require more significant power-grid/design modifications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive assigned blocks/subsystems toward EMIR signoff and design convergence, while meeting project quality and schedule requirements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop and improve automation for EMIR flow execution, data processing, analysis, debug, and reporting.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate effectively with cross-functional teams and provide technical guidance and support on EMIR related issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Contribute to continuous improvement of EMIR methodologies, checks, best practices, and design closure processes.</li></ul>PREFERRED EXPERIENCE:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">4 +Years of hands-on experience in ASIC/SoC Physical Design with significant experience in EMIR analysis and signoff.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong hands-on experience with Ansys RedHawk-SC and/or Cadence Voltus for Electromigration and IR-drop analysis. Experience with both tools is highly preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of Power Delivery Networks (PDN), static IR drop, dynamic IR drop, Electromigration, current density, and power-grid reliability.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with EMIR flow setup, database validation, debug, analysis, and signoff closure.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of the impact of floorplan, placement, routing, power-grid design, vias, and bumps on EMIR.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in debugging EMIR violations and providing effective and practical design recommendations for issue resolution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of multi-voltage designs, voltage islands, and power-domain interactions.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience in power-grid robustness analysis and validation and identifying potential design weaknesses early in the implementation cycle.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with physical design inputs and data such as LEF/DEF, parasitics, power/activity data, technology files, power intent, and design databases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good understanding of the overall ASIC Physical Design flow from floorplanning through implementation, ECO, and signoff.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with scripting languages such as Python, Tcl, Perl, and/or Shell for flow automation, data analysis, reporting, and productivity improvement.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience working on advanced-node, high-performance, or large-scale SoC designs is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with hierarchical/block-to-top EMIR analysis methodologies is an added advantage.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to chip/package power-integrity interactions, bump planning, and package-related power delivery considerations is preferred.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to independently analyze large amounts of EMIR data, identify trends and systematic issues, and drive corrective actions.</li></ul>ACADEMIC CREDENTIALS:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering,  VLSI, Microelectronics, or a related discipline.#LI-SR5</li></ul>

Collected experience requirement

4+ years