RTL DESIGN ENGINEER

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 93026

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. RTL DESIGN ENGINEER <span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335551550":2,"335551620":2,"335559739":0,"335559740":240}"> THE ROLE:As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. THE PERSON:<div class="x_elementToProof" data-ogsc="rgb(0, 0, 0)" data-olk-copy-source="MessageBody">We are seeking an enthusiastic and skilled Design Engineer to join the team within AMD’s Adaptive & Embedded Computing Group (AECG). In this role, you will be part of a team responsible for architecting, designing, and verifying critical on-chip debug, instrumentation, and testability deployed across AMD's industry-leading FPGA, Adaptive SoC (Versal, Zynq UltraScale+), and custom silicon platforms. You will work across both RTL design and functional verification flows, collaborating closely with software, emulation, and silicon bring-up teams.</div> KEY RESPONSIBILITIES:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">RTL Design & Integration:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Design, enhance, and integrate digital IP blocks and subsystems using Verilog / SystemVerilog.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Work on on-chip debug architectures, JTAG/Boundary-Scan controllers (IEEE 1149.1/1500/1687), data movement datapaths, and packetized debug protocols.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Implement and maintain Vivado IP packaging, parameterization, and timing constraints (XDC/SDC).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Design Verification:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Develop and maintain modular, reusable testbenches in SystemVerilog / UVM.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Write test plans, functional assertions (SVA), and covergroups based on architectural specifications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Execute constrained-random verification, analyze code/functional coverage, and root-cause RTL bugs.</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Silicon Validation & Toolchain Integration:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Support pre-silicon emulation (e.g., HAPS/Zebu) and FPGA prototyping environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Assist in lab bring-up, hardware-software co-verification, and debug tool validation (Vivado Lab Edition, Chipscopy, XSDB).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Collaborate with cross-functional teams (Silicon Architecture, Software Tools, Product Applications) to validate IP performance and ease of use. </li></ul></ul> PREFERRED EXPERIENCE:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Experience: 1 – 2 years of relevant industry experience in ASIC/FPGA digital design and verification.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">RTL & Architecture:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Strong foundation in digital design concepts, synchronous design, clock domain crossing (CDC), and timing closure fundamentals.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Proficiency in Verilog / SystemVerilog.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Exposure to standard bus protocols (AXI, APB, AHB) and debug interfaces (JTAG, BSCAN, CoreSight).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Verification:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Hands-on experience building testbenches and writing testcases using SystemVerilog / UVM.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Experience with standard EDA simulation tools (VCS, Questa/ModelSim, or Xcelium).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Understanding of coverage metrics (functional coverage, statement/branch/toggle coverage).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Scripting & Automation:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Basic scripting proficiency in Python, Tcl, Bash, or Perl for test automation and flow integration</li></ul></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in Electronics/Electrical Engineering, VLSI</li></ul> #LI_SG2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

RTL DESIGN ENGINEER <span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335551550":2,"335551620":2,"335559739":0,"335559740":240}"> THE ROLE:As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence.   THE PERSON:<div class="x_elementToProof" data-ogsc="rgb(0, 0, 0)" data-olk-copy-source="MessageBody">We are seeking an enthusiastic and skilled Design Engineer to join the team within AMD’s Adaptive & Embedded Computing Group (AECG). In this role, you will be part of a team responsible for architecting, designing, and verifying critical on-chip debug, instrumentation, and testability deployed across AMD's industry-leading FPGA, Adaptive SoC (Versal, Zynq UltraScale+), and custom silicon platforms. You will work across both RTL design and functional verification flows, collaborating closely with software, emulation, and silicon bring-up teams.</div> KEY RESPONSIBILITIES:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">RTL Design & Integration:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Design, enhance, and integrate digital IP blocks and subsystems using Verilog / SystemVerilog.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Work on on-chip debug architectures, JTAG/Boundary-Scan controllers (IEEE 1149.1/1500/1687), data movement datapaths, and packetized debug protocols.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Implement and maintain Vivado IP packaging, parameterization, and timing constraints (XDC/SDC).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Design Verification:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Develop and maintain modular, reusable testbenches in SystemVerilog / UVM.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Write test plans, functional assertions (SVA), and covergroups based on architectural specifications.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Execute constrained-random verification, analyze code/functional coverage, and root-cause RTL bugs.</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Silicon Validation & Toolchain Integration:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Support pre-silicon emulation (e.g., HAPS/Zebu) and FPGA prototyping environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Assist in lab bring-up, hardware-software co-verification, and debug tool validation (Vivado Lab Edition, Chipscopy, XSDB).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Collaborate with cross-functional teams (Silicon Architecture, Software Tools, Product Applications) to validate IP performance and ease of use. </li></ul></ul> PREFERRED EXPERIENCE:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Experience: 1 – 2 years of relevant industry experience in ASIC/FPGA digital design and verification.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">RTL & Architecture:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Strong foundation in digital design concepts, synchronous design, clock domain crossing (CDC), and timing closure fundamentals.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Proficiency in Verilog / SystemVerilog.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Exposure to standard bus protocols (AXI, APB, AHB) and debug interfaces (JTAG, BSCAN, CoreSight).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Verification:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Hands-on experience building testbenches and writing testcases using SystemVerilog / UVM.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Experience with standard EDA simulation tools (VCS, Questa/ModelSim, or Xcelium).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Understanding of coverage metrics (functional coverage, statement/branch/toggle coverage).</li></ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)"><div class="x_elementToProof" role="presentation" data-ogsc="">Scripting & Automation:</div></li><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-ogsc="rgb(0, 0, 0)">Basic scripting proficiency in Python, Tcl, Bash, or Perl for test automation and flow integration</li></ul></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in Electronics/Electrical Engineering, VLSI</li></ul>  #LI_SG2

Collected experience requirement

1 year