CPU/Cores Post‑Silicon Validation (Security)

AMD · Bangalore

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 92799

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. Cores Post‑Silicon Validation (Security)<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="2" data-aria-level="1">THE ROLEThe AMD Cores Validation team is looking for a highly motivated engineer to drive post-silicon validation of CPU security features across next-generation x86 processor products. The engineer will be responsible for validating architectural and microarchitectural security capabilities, developing security-focused test methodologies, executing validation plans, and driving complex debug activities from first silicon through production readiness.This role provides an opportunity to work closely with Architecture, Design, Firmware, Security, and Product Engineering teams to ensure robust implementation of processor security technologies. KEY RESPONSIBILITIES<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop and execute post-silicon validation plans for CPU security features.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate architectural security capabilities including: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure Virtual Machine (SVM)</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">SEV / SEV-ES / SEV-SNP</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Memory encryption technologies</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure Boot</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Trusted execution and attestation mechanisms</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Speculation and side-channel mitigation features</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Virtualization security extensions</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Design directed and stress workloads to verify security functionality, robustness, and corner-case behavior.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform silicon bring-up and feature enablement on pre-production platforms.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Debug failures spanning: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">CPU cores and microarchitecture</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Microcode (uCode)</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">BIOS/Firmware</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Security processors and firmware</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze logs, machine check data, MSRs, traces, and hardware debug information to isolate root causes.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with Design, Architecture, Security, and Firmware teams to drive issue resolution.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop automation infrastructure to improve validation efficiency, coverage, and regression execution.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Track validation coverage, defect metrics, and readiness criteria for product milestones.</li></ul> REQUIRED QUALIFICATIONS<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of computer architecture and x86 processors.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good knowledge of operating systems internals and virtualization technologies.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with processor security concepts such as: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Encryption</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Authentication</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure boot flows</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Trust chains</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Isolation mechanisms</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Virtualization security</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with silicon validation, system validation, or hardware validation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong debug and root-cause analysis skills.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proficiency in Python, C/C++, or scripting languages for automation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience working in Linux and Windows environments.</li></ul> PREFERRED QUALIFICATIONS<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Prior experience in CPU cores post-silicon validation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience validating security IPs or processor security features.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of SEV, SNP, TSME, SME, Secure Boot, PSP/ASP architectures, or trusted execution technologies.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understanding of cache hierarchy, memory management, coherency protocols, and microarchitectural behavior.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with microcode, BIOS, firmware, and platform bring-up flows.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to security testing methodologies including penetration, negative, and adversarial validation approaches.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon debug tools, JTAG, trace, and performance monitoring infrastructure.</li></ul> </li></ul> ACADEMIC CREDENTIALS: <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering or related field</li></ul> #LI-DB2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

Cores Post‑Silicon Validation (Security)<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="10" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="2" data-aria-level="1">THE ROLEThe AMD Cores Validation team is looking for a highly motivated engineer to drive post-silicon validation of CPU security features across next-generation x86 processor products. The engineer will be responsible for validating architectural and microarchitectural security capabilities, developing security-focused test methodologies, executing validation plans, and driving complex debug activities from first silicon through production readiness.This role provides an opportunity to work closely with Architecture, Design, Firmware, Security, and Product Engineering teams to ensure robust implementation of processor security technologies. KEY RESPONSIBILITIES<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop and execute post-silicon validation plans for CPU security features.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate architectural security capabilities including: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure Virtual Machine (SVM)</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">SEV / SEV-ES / SEV-SNP</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Memory encryption technologies</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure Boot</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Trusted execution and attestation mechanisms</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Speculation and side-channel mitigation features</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Virtualization security extensions</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Design directed and stress workloads to verify security functionality, robustness, and corner-case behavior.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform silicon bring-up and feature enablement on pre-production platforms.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Debug failures spanning: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">CPU cores and microarchitecture</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Microcode (uCode)</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">BIOS/Firmware</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Security processors and firmware</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze logs, machine check data, MSRs, traces, and hardware debug information to isolate root causes.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with Design, Architecture, Security, and Firmware teams to drive issue resolution.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop automation infrastructure to improve validation efficiency, coverage, and regression execution.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Track validation coverage, defect metrics, and readiness criteria for product milestones.</li></ul> REQUIRED QUALIFICATIONS<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or related field.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong understanding of computer architecture and x86 processors.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Good knowledge of operating systems internals and virtualization technologies.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with processor security concepts such as: </li><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="circle"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Encryption</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Authentication</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Secure boot flows</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Trust chains</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Isolation mechanisms</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Virtualization security</li></ul><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with silicon validation, system validation, or hardware validation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong debug and root-cause analysis skills.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proficiency in Python, C/C++, or scripting languages for automation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience working in Linux and Windows environments.</li></ul> PREFERRED QUALIFICATIONS<ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Prior experience in CPU cores post-silicon validation.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience validating security IPs or processor security features.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of SEV, SNP, TSME, SME, Secure Boot, PSP/ASP architectures, or trusted execution technologies.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understanding of cache hierarchy, memory management, coherency protocols, and microarchitectural behavior.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with microcode, BIOS, firmware, and platform bring-up flows.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Exposure to security testing methodologies including penetration, negative, and adversarial validation approaches.</li><li style="margin-top: 0px; margin-bottom: 0px; vertical-align: middle; font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with post-silicon debug tools, JTAG, trace, and performance monitoring infrastructure.</li></ul>  </li></ul>  ACADEMIC CREDENTIALS:  <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering or related field</li></ul>  #LI-DB2