Senior RTL Silicon Design & Validation Engineer

AMD · Hyderabad

Source and collection record

Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 79743

Job type and experience labels are automated discovery categories. The employer determines eligibility. Original experience wording was not retained separately; check the current employer page.

How sourcing and classification work · Report a discrepancy

Your application evidence checklist

Mark the statements you can support after reading the employer source. This checklist stays on this page; it does not score your eligibility or submit an application.

Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. As a member of the AECG Product Validation and Solutions Team within AMD, you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High-speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen6/Gen7, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges. KEY RESPONSIBILITIES: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: #262626;">Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets</li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Pre-Silicon and Post Silicon validation for new PCIe enabled blocks</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Responsible for IP design, Silicon bring up, Validation and IP release </li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Work in collaboration with the Global teams</li></ul> PREFERRED EXPERIENCE: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Proficient in RTL simulation tools (VCS, Modelsim)</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM, AMBA AXI/AHB/APB protocol</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience in developing system or IP prototypes using FPGAs</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong knowledge of IP/SOC design methodologies</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Knowledge of C/C++ is an added advantage</li></ul> ACADEMIC CREDENTIALS: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Bachelor's or Masters degree in Computer Engineering/Electrical Engineering with 8+Yrs of exp</li></ul> #LI-DB2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

As a member of the AECG Product Validation and Solutions Team within AMD, you will develop and enable the next generation of PCIe technologies to power datacenter, acceleration, AI and communications markets. High-speed PCIe connectivity is critical for modern technology and infrastructure that helps improve our lives. THE ROLE: At AMD you will help create leading edge PCIe technologies used in a wide variety of applications. The focus of this role is to design, plan and execute RTL design for new and existing PCIe technology and solutions for programmable silicon at AMD. Key development includes PCIe technologies for PCIe Gen6/Gen7, CXL, TDISP, IDE, PCIe in-line DMA and other leading edge products. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. You should also have a desire to expand existing skill sets and take on new challenges.  KEY RESPONSIBILITIES: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: #262626;">Develop and productize next generation PCIe, CXL and connectivity solutions to power datacenter, acceleration, AI and communications markets</li></ul><ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Participate in technical role in all phases of the product development cycle from new product exploration, architecture through implementation, prototyping, validation, productization and support including but not limited to architecture, design, and documentation for IPs</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Develop comprehensive testing plans including Compliance and Interop testing. Critically review and provide feedback on the Design Implementations and Verification plans</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Pre-Silicon and Post Silicon validation for new PCIe enabled blocks</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Responsible for IP design, Silicon bring up, Validation and IP release </li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Work in collaboration with the Global teams</li></ul> PREFERRED EXPERIENCE: <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong knowledge in RTL coding, preferably with Verilog and SystemVerilog</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Proficient in RTL simulation tools (VCS, Modelsim)</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Knowledge of high-speed interfaces including, PCIe, CXL, NVMe, Ethernet, DDR3/4/5, LPDDR3/4, HBM,  AMBA AXI/AHB/APB protocol</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience in using Lab equipment like PCIe Lecroy/Viavi Exerciser/Analyzer</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience in developing system or IP prototypes using FPGAs</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Strong knowledge of IP/SOC design methodologies</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Experience with scripting languages including Tcl, Perl, Python, Unix shells and Makefiles</li><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Knowledge of C/C++ is an added advantage</li></ul>  ACADEMIC CREDENTIALS:  <ul style="direction: ltr; unicode-bidi: embed; margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0; margin-bottom: 0; vertical-align: middle; color: black;">Bachelor's or Masters degree in Computer Engineering/Electrical Engineering with 8+Yrs of exp</li></ul> #LI-DB2

Collected experience requirement

8+ years