PD IREM LEAD

<strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">WHAT YOU DO AT AMD CHANGES EVERYTHING</span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p><p style="margin: 0px; padding: 0px; color: windowtext;"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, </span><span style="margin: 0px; padding: 0px;">gaming</span><span style="margin: 0px; padding: 0px;"> and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human </span><span style="margin: 0px; padding: 0px; border-bottom: 1px solid transparent;">ingenuity</span><span style="margin: 0px; padding: 0px;"> and a shared passion to create something extraordinary. When you join AMD, </span><span style="margin: 0px; padding: 0px;">you’ll</span><span style="margin: 0px; padding: 0px;"> discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.</span><span style="margin: 0px; padding: 0px;"> </span></span><strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-contrast="auto"><span style="margin: 0px; padding: 0px;">Together, we advance your career. </span></span></strong><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSCustomFont, Arial_MSFontService, sans-serif;" data-ccp-props="{}"> </span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px; padding: 0px; color: windowtext;"><strong><span style="margin: 0px; padding: 0px; color: #32363a; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-contrast="none"><span style="margin: 0px; padding: 0px;"> </span></span></strong></p><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">🔹</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> THE ROLE</span></strong></p><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">As a <strong>PHY‑V Lead</strong>, you will own <strong>physical verification sign-off, full-chip integration, and packaging interface (RDL) planning</strong> for advanced SoC programs. You will drive <strong>DRC/LVS clean tapeouts, integration quality, and sign-off predictability</strong> across complex multi-IP designs.</span></p><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">This role requires strong expertise in <strong>physical verification, top-level integration, and advanced packaging alignment</strong>, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.</span></p><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">🔹</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> THE PERSON</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Strong technical leader with <strong>deep PD + Physical Verification understanding</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Proven ownership of <strong>sign-off closure for complex SoCs</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Ability to drive execution across <strong>multiple teams and dependencies</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Detail-oriented with focus on <strong>quality, manufacturability, and schedule predictability</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Comfortable operating in <strong>high-pressure tapeout environments</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">🔹</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> KEY RESPONSIBILITIES</span></strong></p><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> Physical Verification & Sign-off Ownership</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Drive end-to-end <strong>DRC, LVS, ERC, antenna closure</strong> at block and full-chip level</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Define and enforce <strong>sign-off methodology and quality criteria</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Own foundry rule decks, waivers, and risk assessments</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Deliver <strong>sign-off clean GDS for tapeout</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> SoC / Full-Chip Integration</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead <strong>top-level integration of IPs/macros into SoC</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Own: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">GDS assembly</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Hierarchical LVS reconciliation</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Resolve: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Boundary issues</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Connectivity mismatches</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Integration conflicts</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Ensure <strong>robust integration across internal and third-party IPs</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> RDL & Packaging Integration</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Drive <strong>RDL planning and bump mapping strategy</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Define IO escape routing and die–package interface</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Collaborate with <strong>Packaging, SI/PI, and system teams</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Enable <strong>flip-chip / 2.5D / 3D integration readiness</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> Tapeout Execution & Tracking</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Own <strong>sign-off checklist, closure tracking, and tapeout readiness</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead <strong>tapeout reviews and milestone tracking</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Drive cross-team closure to meet <strong>schedule and quality targets</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> Methodology & Flow Development</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Define and improve <strong>physical verification flows (Calibre/ICV/Pegasus)</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Drive: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Automation (TCL/Python)</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Runtime optimization</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Debug efficiency</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Establish best practices for <strong>hierarchical and incremental sign-off</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> Debug & Issue Resolution</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead debug of: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Complex DRC violations</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">LVS mismatches (shorts/opens/connectivity issues)</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Drive closure with PD/layout teams</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Minimize waivers and ensure <strong>risk-managed sign-off</strong></span></li></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">✅</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> Leadership & Collaboration</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Lead and mentor PHY‑V engineers</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Act as <strong>primary escalation point for sign-off issues</strong></span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Interface with: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">PD / PnR teams</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Analog/layout teams</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Packaging and foundry teams</span></li></ul></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">🔹</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> REQUIRED QUALIFICATIONS</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">B.Tech / M.Tech in Electronics / Electrical Engineering</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">10–15+ years</span></strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> in Physical Design / Physical Verification / SoC Integration</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Strong expertise in: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">DRC, LVS, ERC, antenna checks</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Tools: <strong>Calibre / ICV / Pegasus</strong></span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Solid understanding of: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Full PD flow (RTL → GDS → sign-off)</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Advanced process nodes (7nm and below)</span></li></ul></ul><div style="text-align: center; margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;" align="center"><hr align="center" size="1" width="100%"></div><p style="margin: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><strong><span style="font-size: 11.0pt; font-family: 'Segoe UI Emoji', sans-serif;">🔹</span></strong><strong><span style="font-size: 11.0pt; font-family: Arial, sans-serif;"> PREFERRED QUALIFICATIONS</span></strong></p><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="disc"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Experience in: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Full-chip SoC integration and GDS assembly</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">RDL planning and advanced packaging flows</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Exposure to: </span></li><ul style="margin-top: 0cm; margin-bottom: 0cm;" type="circle"><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">IR/EM, SI/PI, PEX, reliability checks</span></li><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Chiplet / 2.5D / 3D-IC methodologies</span></li></ul><li style="margin-top: 0cm; margin-right: 0cm; margin-bottom: 0cm; font-size: 12pt; font-family: Aptos, sans-serif;"><span style="font-size: 11.0pt; font-family: Arial, sans-serif;">Strong scripting (TCL/Python) for automation</span></li></ul><p> </p><ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 11pt; font-family: Calibri, Calibri_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"><span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-BM2 </span></li></ul> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>