Senior FPGA IP Design engineer

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 91914

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career. THE ROLE: The focus of this role is to plan, build, and execute the end-to-end processing system solution THE PERSON: Looking for highly motivated and self-driven engineer KEY RESPONSIBILITIES: <ul><li>Will be responsible for planning and execution of end-to-end processing system solution including Vivado IP configuration to software execution targeting customer usecases on AMD Xilinx products</li><li>Collaborate with marketing, architects, hardware engineers, pre/post silicon verification and firmware engineers to define specification and implementation of processing system solution requirements with agreed scope and timelines</li><li>Work closely with your team and cross site stakeholders to drive the requirements and deliverables</li><li>Interact with multiple teams across AMD to develop processing IP solution targeting AMD AECG FPGA/SoC/ACAP solution, including bare metal and OS hosted environments</li></ul>PREFERRED EXPERIENCE: <ul><li>Self-driven, motivated, focused, results oriented individual with superior academic achievements</li><li>Excellent communication skill for working remotely with global team</li><li>Proficient knowledge of Verilog/system verilog coding, and simulation (Xilinx simulator, ModelSim, NC-Verilog, VCS etc.)</li><li>Understanding FPGA basics, FPGA tools flow, using AMD Xilinx/AECG FPGAs, FPGA timing constraints, STA and timing closure</li><li>Knowledge of system-level architecture including buses like AXI, bridges, memory controllers , High Speed serial connectivity, PCIe, Ethernet etc is a plus.</li><li>Good understanding of processing system, boot and IO peripherals is preferable</li><li>Good organizational skills with ability to multi-task, prioritize, and track many activities.</li><li>Very good collaboration skills to interface with architecture, design and validation teams.</li><li>Expertise in debugging systems on boards using debugger/scopes</li><li>Ability to drive hardware/software solution projects at all stages from planning to implementation</li><li>Familiar with Xilinx SDX tools to create software application is a plus</li><li>Programming languages familiarity is a plus: C, Assembly, embedded applications programming</li><li>Scripting: very good knowledge in Tcl/Python/PERL/C-Shell</li><li>Understanding of GT Transceivers/SERDES is a plus</li><li>Very good team player</li></ul>ACADEMIC CREDENTIALS: <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><ul><li>M.S/M.Tech/B.E/B.S/B.Tech in EE/ECE/CSE with at least 6+ years of experience in IP/Sub-system/System development and validation</li></ul></li></ul>#LI-SR4 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE: The focus of this role is to plan, build, and execute the end-to-end processing system solution  THE PERSON:  Looking for highly motivated and self-driven engineer  KEY RESPONSIBILITIES:  <ul><li>Will be responsible for planning and execution of end-to-end processing system solution including Vivado IP configuration to software execution targeting customer usecases on AMD Xilinx products</li><li>Collaborate with marketing, architects, hardware engineers, pre/post silicon verification and firmware engineers to define specification and implementation of processing system solution requirements with agreed scope and timelines</li><li>Work closely with your team and cross site stakeholders to drive the requirements and deliverables</li><li>Interact with multiple teams across AMD to develop processing IP solution targeting AMD AECG FPGA/SoC/ACAP solution, including bare metal and OS hosted environments</li></ul>PREFERRED EXPERIENCE:  <ul><li>Self-driven, motivated, focused, results oriented individual with superior academic achievements</li><li>Excellent communication skill for working remotely with global team</li><li>Proficient knowledge of Verilog/system verilog coding, and simulation (Xilinx simulator, ModelSim, NC-Verilog, VCS etc.)</li><li>Understanding FPGA basics, FPGA tools flow, using AMD Xilinx/AECG FPGAs, FPGA timing constraints, STA and timing closure</li><li>Knowledge of system-level architecture including buses like AXI, bridges, memory controllers , High Speed serial connectivity, PCIe, Ethernet etc is a plus.</li><li>Good understanding of processing system, boot and IO peripherals is preferable</li><li>Good organizational skills with ability to multi-task, prioritize, and track many activities.</li><li>Very good collaboration skills to interface with architecture, design and validation teams.</li><li>Expertise in debugging systems on boards using debugger/scopes</li><li>Ability to drive hardware/software solution projects at all stages from planning to implementation</li><li>Familiar with Xilinx SDX tools to create software application is a plus</li><li>Programming languages familiarity is a plus: C, Assembly, embedded applications programming</li><li>Scripting: very good knowledge in Tcl/Python/PERL/C-Shell</li><li>Understanding of GT Transceivers/SERDES is a plus</li><li>Very good team player</li></ul>ACADEMIC CREDENTIALS:  <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><ul><li>M.S/M.Tech/B.E/B.S/B.Tech in EE/ECE/CSE with at least 6+ years of experience in IP/Sub-system/System development and validation</li></ul></li></ul>#LI-SR4

Collected experience requirement

6+ years