SoC Physical Design Lead

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 88978

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. THE ROLE:We are seeking a seasoned SoC PD lead with expertise in delivering high-quality physical design implementations that meet PPA and schedule targets, contribute to physical design innovation, influencing multiple programs and organizational decisions, meticulous about Power, Performance and Area while driving schedule and managing cost. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: <ul><li>Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.</li><li>Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).</li><li>Establish and drive sign-off criteria and waiver processes.</li><li>Introduce innovative techniques for congestion management, timing optimization, and power integrity.</li><li>Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.</li><li>Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.</li><li>Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.</li><li>Publish risk burndown reports and mitigation plans for tapeout-critical paths.</li><li>Lead technical reviews and provide consultative input to management on design trade-offs.</li><li>Work closely with Design teams for Area and Floorplan refinement, Timing targets, Pre-Si bug resolution and PPA sign-off.</li></ul> PREFERRED EXPERIENCE:<ul><li>15+ Years of experience in relevant domain.</li><li>Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.</li><li>Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks & Resets.</li><li>Excellent communication, management, and presentation skills. </li><li>Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies </li></ul> ACADEMIC CREDENTIALS:<ul><li>Bachelors or Masters degree in computer engineering/Electrical Engineering c</li></ul>#LI-NS1 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

THE ROLE:We are seeking a seasoned SoC PD lead with expertise in delivering high-quality physical design implementations that meet PPA and schedule targets, contribute to physical design innovation, influencing multiple programs and organizational decisions, meticulous about Power, Performance and Area while driving schedule and managing cost. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.  KEY RESPONSIBILITIES: <ul><li>Own end-to-end physical design for high-performance, low-power SoCs, including floorplanning, placement, clock tree synthesis, routing, and timing closure.</li><li>Define and optimize PnR strategies for advanced nodes (e.g., 5nm/3nm/2nm), balancing performance, power, and area (PPA).</li><li>Establish and drive sign-off criteria and waiver processes.</li><li>Introduce innovative techniques for congestion management, timing optimization, and power integrity.</li><li>Partner with RTL, architecture, CAD, and verification teams to resolve design challenges and ensure seamless integration.</li><li>Influence design partitioning, interface planning, and hierarchical strategies to meet aggressive schedules.</li><li>Anticipate schedule risks tied to ECO delivery and resource constraints; implement prefetch and compliance gates for ECO readiness.</li><li>Publish risk burndown reports and mitigation plans for tapeout-critical paths.</li><li>Lead technical reviews and provide consultative input to management on design trade-offs.</li><li>Work closely with Design teams for Area and Floorplan refinement, Timing targets, Pre-Si bug resolution and PPA sign-off.</li></ul> PREFERRED EXPERIENCE:<ul><li>15+ Years of experience in relevant domain.</li><li>Proficient in Working with various EDA tools. Innovus, Fusion compiler/ICCompiler2, Primetime etc.</li><li>Foundational experience in SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks & Resets.</li><li>Excellent communication, management, and presentation skills. </li><li>Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies </li></ul> ACADEMIC CREDENTIALS:<ul><li>Bachelors or Masters degree in computer engineering/Electrical Engineering c</li></ul>#LI-NS1

Collected experience requirement

15+ years