Lead/Staff AI/ML Validation Engineer

AMD · Bangalore

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 87968

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. <div><h2>Role Overview</h2>We are seeking an experienced SMTS Software Quality Engineer to join the HIP Runtime Quality Engineering team within the ROCm ecosystem. In this role, you will focus on defect triage, root‑cause analysis, and scalable test automation for the HIP runtime, ensuring robustness, portability, and performance across AMD and NVIDIA GPU backends.The role sits at the intersection of runtime systems, GPU APIs, and CI-driven quality assurance, working closely with HIP runtime developers, compiler teams, and system software engineers to improve test coverage and accelerate issue resolution across a fast-evolving open‑source stack.HIP is a C++ runtime API and kernel language designed for CUDA portability and heterogeneous GPU programming in the ROCm platform.<hr><h2>Key Responsibilities</h2><h3>Defect Triage & Root Cause Analysis</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Own end-to-end triage of HIP runtime failures observed in CI, nightly, and release testing pipelines.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze failures across HIP runtime APIs, including memory management, streams, events, kernels, graphs, and device management.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform log analysis, repro reduction, and backtrace debugging across Linux and Windows environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Correlate failures across:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">ROCr system runtime</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">HIP runtime</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Driver / firmware interfaces</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Compiler (hipcc / clang) interactions</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">File high‑quality bug reports with clear reproduction steps, root cause hypotheses, and impact assessment.</li></ul><hr><h3>Test Automation & Framework Development</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Design, enhance, and maintain automated test frameworks for HIP runtime validation using existing HIP test infrastructure (Catch2-based and custom harnesses).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expand functional, negative, stress, and regression coverage for:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">HIP Runtime APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Graph APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Memory copy variants (1D/2D/3D, async/sync)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Multi-GPU and peer-to-peer use cases</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Integrate tests into CI/CD pipelines with actionable failure reporting.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop Python, C++, and shell-based automation for test execution, result aggregation, and trend analysis.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive test flakiness reduction and improve signal-to-noise ratio in large-scale CI.</li></ul><hr><h3>Cross-Team Collaboration</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Partner with HIP runtime developers to:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Review test gaps for new features and APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate bug fixes and performance-sensitive code paths</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Compiler and language runtime teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">ROCr system runtime teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Release engineering and CI infrastructure teams</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Contribute test fixes and enhancements upstream in open-source HIP/ROCm repositories.</li></ul><hr><h3>Quality Metrics & Continuous Improvement</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define and track quality metrics such as failure escape rate, test coverage, and mean-time-to-resolution (MTTR).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify systemic issues and propose data-driven quality improvements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Participate in release readiness assessments for HIP runtime drops.</li></ul><hr><h2>Required Qualifications</h2><h3>Technical Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong experience in software quality engineering, test automation, or SDET roles.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Solid proficiency in C++ with debugging experience (gdb/lldb).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Working knowledge of HIP or CUDA runtime concepts, including kernels, streams, memory models, and device execution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with Linux-based development and debugging.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with CI systems (Jenkins, GitHub Actions, GitLab CI, or similar).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience writing and maintaining automated tests for low-level systems or runtime libraries.</li></ul><hr><h3>Debugging & Analysis Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to reason about runtime abstractions, concurrency, and asynchronous execution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong skills in failure reproduction, minimization, and log-driven debugging.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience triaging issues across hardware–software boundaries is a plus.</li></ul><hr><h2>Preferred Qualifications</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with GPU programming models (HIP, CUDA, OpenCL).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with ROCm stack components (HIP, ROCr, compilers, drivers).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience testing graph APIs, async execution models, or multi-GPU systems.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Prior contributions to open-source system software or test frameworks.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of Python-based test orchestration and reporting tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge and application of AI tools in validation and testing.</li></ul><hr><h2>What Success Looks Like</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Faster, higher-quality issue triage with actionable root cause insights.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Improved automation coverage for HIP runtime APIs and edge cases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Reduced CI noise and faster feedback for developers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong collaboration with runtime and compiler engineers to ship stable, high-quality HIP releases.</li></ul></div> #LI-NR1 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<div><h2>Role Overview</h2>We are seeking an experienced SMTS Software Quality Engineer to join the HIP Runtime Quality Engineering team within the ROCm ecosystem. In this role, you will focus on defect triage, root‑cause analysis, and scalable test automation for the HIP runtime, ensuring robustness, portability, and performance across AMD and NVIDIA GPU backends.The role sits at the intersection of runtime systems, GPU APIs, and CI-driven quality assurance, working closely with HIP runtime developers, compiler teams, and system software engineers to improve test coverage and accelerate issue resolution across a fast-evolving open‑source stack.HIP is a C++ runtime API and kernel language designed for CUDA portability and heterogeneous GPU programming in the ROCm platform.<hr><h2>Key Responsibilities</h2><h3>Defect Triage & Root Cause Analysis</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Own end-to-end triage of HIP runtime failures observed in CI, nightly, and release testing pipelines.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Analyze failures across HIP runtime APIs, including memory management, streams, events, kernels, graphs, and device management.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Perform log analysis, repro reduction, and backtrace debugging across Linux and Windows environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Correlate failures across:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">ROCr system runtime</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">HIP runtime</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Driver / firmware interfaces</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Compiler (hipcc / clang) interactions</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">File high‑quality bug reports with clear reproduction steps, root cause hypotheses, and impact assessment.</li></ul><hr><h3>Test Automation & Framework Development</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Design, enhance, and maintain automated test frameworks for HIP runtime validation using existing HIP test infrastructure (Catch2-based and custom harnesses).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expand functional, negative, stress, and regression coverage for:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">HIP Runtime APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Graph APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Memory copy variants (1D/2D/3D, async/sync)</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Multi-GPU and peer-to-peer use cases</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Integrate tests into CI/CD pipelines with actionable failure reporting.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Develop Python, C++, and shell-based automation for test execution, result aggregation, and trend analysis.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive test flakiness reduction and improve signal-to-noise ratio in large-scale CI.</li></ul><hr><h3>Cross-Team Collaboration</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Partner with HIP runtime developers to:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Review test gaps for new features and APIs</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Validate bug fixes and performance-sensitive code paths</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with:<ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Compiler and language runtime teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">ROCr system runtime teams</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Release engineering and CI infrastructure teams</li></ul></li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Contribute test fixes and enhancements upstream in open-source HIP/ROCm repositories.</li></ul><hr><h3>Quality Metrics & Continuous Improvement</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define and track quality metrics such as failure escape rate, test coverage, and mean-time-to-resolution (MTTR).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Identify systemic issues and propose data-driven quality improvements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Participate in release readiness assessments for HIP runtime drops.</li></ul><hr><h2>Required Qualifications</h2><h3>Technical Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong experience in software quality engineering, test automation, or SDET roles.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Solid proficiency in C++ with debugging experience (gdb/lldb).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Working knowledge of HIP or CUDA runtime concepts, including kernels, streams, memory models, and device execution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with Linux-based development and debugging.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with CI systems (Jenkins, GitHub Actions, GitLab CI, or similar).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience writing and maintaining automated tests for low-level systems or runtime libraries.</li></ul><hr><h3>Debugging & Analysis Skills</h3><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to reason about runtime abstractions, concurrency, and asynchronous execution.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong skills in failure reproduction, minimization, and log-driven debugging.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience triaging issues across hardware–software boundaries is a plus.</li></ul><hr><h2>Preferred Qualifications</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with GPU programming models (HIP, CUDA, OpenCL).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Familiarity with ROCm stack components (HIP, ROCr, compilers, drivers).</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience testing graph APIs, async execution models, or multi-GPU systems.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Prior contributions to open-source system software or test frameworks.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge of Python-based test orchestration and reporting tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Knowledge and application of AI tools in validation and testing.</li></ul><hr><h2>What Success Looks Like</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Faster, higher-quality issue triage with actionable root cause insights.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Improved automation coverage for HIP runtime APIs and edge cases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Reduced CI noise and faster feedback for developers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong collaboration with runtime and compiler engineers to ship stable, high-quality HIP releases.</li></ul></div> #LI-NR1