Senior SoC Design Verification Engineer

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 89842

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. SENIOR SILICON DESIGN VERIFICATION ENGINEER THE ROLE: <div>The SMTS SoC Design Verification Engineer is responsible for leading the verification of complex SoC features and subsystems, driving verification methodology, ensuring high-quality silicon sign-off, and mentoring engineers across the verification organization. The role requires deep expertise in SoC architecture, System Verilog/UVM, debug, coverage closure, and cross-functional collaboration</div><span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|79","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> KEY RESPONSIBLITIES: <div><div> </div></div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Own end-to-end verification of key SoC features and system-level scenarios.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Develop and execute comprehensive verification plans, testbenches, and regression strategies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive functional, code, assertion, and scenario coverage closure.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Lead SoC/IP integration verification and sign-off activities.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Debug complex RTL, architecture, testbench, and firmware issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Collaborate closely with Architecture, RTL, Firmware, Emulation, Platform, and Validation teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive verification methodology improvements, automation, and productivity enhancements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Support pre-silicon bring-up, emulation, and post-silicon debug activities.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Mentor and technically guide MTS/SDE engineers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive execution toward program milestones such as LSB, LSC, LSD, and Tape-Out</li></ul> PREFERRED EXPERIENCE: <div><div> Minimum 12+ years of experience in ASIC Design Verification</div></div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Experiance in X86 based SOC DV</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Strong expertise in SoC verification methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Advanced SystemVerilog and UVM knowledge.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Experience with SoC/IP verification environments, VIPs, UVCs, BFMs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Strong debugging skills using industry-standard simulation and verification tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Knowledge of functional and code coverage methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Understanding of SoC architecture, interconnects, memory subsystems, security, power management, and performance features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Familiarity with scripting (Python/Perl/Shell), regression automation, and version control systems.</li></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 14pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in Electronics engineering </li></ul> #LI-PK2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

SENIOR SILICON DESIGN VERIFICATION ENGINEER THE ROLE:  <div>The SMTS SoC Design Verification Engineer is responsible for leading the verification of complex SoC features and subsystems, driving verification methodology, ensuring high-quality silicon sign-off, and mentoring engineers across the verification organization. The role requires deep expertise in SoC architecture, System Verilog/UVM, debug, coverage closure, and cross-functional collaboration</div><span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|79","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> KEY RESPONSIBLITIES: <div><div> </div></div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Own end-to-end verification of key SoC features and system-level scenarios.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Develop and execute comprehensive verification plans, testbenches, and regression strategies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive functional, code, assertion, and scenario coverage closure.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Lead SoC/IP integration verification and sign-off activities.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Debug complex RTL, architecture, testbench, and firmware issues.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Collaborate closely with Architecture, RTL, Firmware, Emulation, Platform, and Validation teams.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive verification methodology improvements, automation, and productivity enhancements.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Support pre-silicon bring-up, emulation, and post-silicon debug activities.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Mentor and technically guide MTS/SDE engineers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Drive execution toward program milestones such as LSB, LSC, LSD, and Tape-Out</li></ul>  PREFERRED EXPERIENCE: <div><div>  Minimum 12+ years of experience in ASIC Design Verification</div></div><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Experiance in X86 based SOC DV</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Strong expertise in SoC verification methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Advanced SystemVerilog and UVM knowledge.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Experience with SoC/IP verification environments, VIPs, UVCs, BFMs.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Strong debugging skills using industry-standard simulation and verification tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Knowledge of functional and code coverage methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Understanding of SoC architecture, interconnects, memory subsystems, security, power management, and performance features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 14pt;">Familiarity with scripting (Python/Perl/Shell), regression automation, and version control systems.</li></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 14pt; font-family: arial, helvetica, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in Electronics engineering </li></ul> #LI-PK2

Collected experience requirement

12+ years