Lead IP Block level Verification Engineer

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 84960

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

0 of 3 checks marked. Keep unresolved requirements as questions for the employer.

Collected role description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}"> THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: <ul><li>Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications</li><li>Interact with architects and design engineers to create a comprehensive verification testplan</li><li>Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner</li><li>Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools</li><li>Debug tests with design engineers to deliver functionally correct design blocks</li><li>Identify and write coverage measures for stimulus quality improvements</li><li>Perform coverage analysis to identify verification holes and achieve closure on coverage metrics </li></ul>PREFERRED EXPERIENCE: <ul style="margin-top: 0in;"><li style="margin-top: 3.75pt;">Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.</li><li style="margin-top: 3.75pt;">Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.</li><li style="margin-top: 3.75pt;">Strong understanding of different phases of ASIC and/or full custom chip development is required.</li><li style="margin-top: 3.75pt;">Experience in block level NOC (Net work on Chip) verification is a plus.</li><li style="margin-top: 3.75pt;">Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.</li><li style="margin-top: 3.75pt;">Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.</li><li style="margin-top: 3.75pt;">Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.</li><li style="margin-top: 3.75pt;">Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.</li><li style="margin-top: 3.75pt;">Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> </li></ul>ACADEMIC CREDENTIALS: <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering<span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> with 8+Yrs of exp</li></ul> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-SR4 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">MTS SILICON DESIGN ENGINEER<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|106","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335551550":2,"335551620":2,"335559738":0,"335559739":0,"335559740":240}">  THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.  THE PERSON:  You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.   KEY RESPONSIBILITIES:  <ul><li>Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications</li><li>Interact with architects and design engineers to create a comprehensive verification testplan</li><li>Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner</li><li>Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools</li><li>Debug tests with design engineers to deliver functionally correct design blocks</li><li>Identify and write coverage measures for stimulus quality improvements</li><li>Perform coverage analysis to identify verification holes and achieve closure on coverage metrics </li></ul>PREFERRED EXPERIENCE:  <ul style="margin-top: 0in;"><li style="margin-top: 3.75pt;">Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.</li><li style="margin-top: 3.75pt;">Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.</li><li style="margin-top: 3.75pt;">Strong understanding of different phases of ASIC and/or full custom chip development is required.</li><li style="margin-top: 3.75pt;">Experience in block level NOC (Net work on Chip) verification is a plus.</li><li style="margin-top: 3.75pt;">Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.</li><li style="margin-top: 3.75pt;">Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.</li><li style="margin-top: 3.75pt;">Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.</li><li style="margin-top: 3.75pt;">Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.</li><li style="margin-top: 3.75pt;">Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> </li></ul>ACADEMIC CREDENTIALS: <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1"><span style="margin: 0px; padding: 0px;" data-ccp-parastyle="paragraph" data-ccp-parastyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|104","ClassId":1073872969,"Properties":[469775450,"paragraph",201340122,"2",134233614,"true",469778129,"paragraph",335572020,"1",469777841,"Times New Roman",469777842,"Times New Roman",469777843,"Times New Roman",469777844,"Times New Roman",469769226,"Times New Roman",268442635,"24",335559740,"240",201341983,"0",134233118,"true",134233117,"true",469778324,"Normal"]}">Bachelors or Masters degree in computer engineering/Electrical Engineering<span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> with 8+Yrs of exp</li></ul> <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-SR4

Collected experience requirement

8+ years