Senior Functional Verification Engineer (Graphics/Multimedia)

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 89783

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. SMTS SILICON DESIGN ENGINEER THE ROLE:<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> As a member of the Client/Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> THE PERSON:<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|78","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|79","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> KEY RESPONSIBLITIES:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Specifying design verification plan at soc level/IP level</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Specifying or reviewing verification plans for complex blocks within the ASIC</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">self-checking, reusable, automated verification environment : both at full-chip & block level</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Constrained random generators and reference models</li></ul></li><li style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;">Carve out the scope and work hands-on on functional verification.Guide/mentor junior members on the teamWork with internal/external stakholders to drive company-wide solutions</li></ul> PREFERRED EXPERIENCE:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Minimum 12+ years of experience in ASIC Design Verification</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Must have excellent knowledge of ASIC Design Flow and SOC architecture</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in developing complex testbench/model in verilog, System verilog or SystemC</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience with coverage-based verification methodology</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in writing testplans and testcases</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Excellent debug skills in functional simulations are must.</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in random test generation, coverage analysis, failure debug</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/shell scripts programming skills.</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Must have very strong communication skills and the ability/desire to foster a team/global environment.</li></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 11pt; font-family: Calibri, Calibri_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in computer engineering/Electrical Engineering<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> </li></ul> <span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-PK2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

SMTS SILICON DESIGN ENGINEER THE ROLE:<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335559739":0,"335559740":240}"> As a member of the Client/Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> THE PERSON:<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|78","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="eop" data-ccp-charstyle-defn="{"ObjectId":"64fd21cd-3dd0-4083-81ca-11a1389a2abb|79","ClassId":1073872969,"Properties":[469775450,"eop",201340122,"1",134233614,"true",469778129,"eop",335572020,"1",469778324,"Default Paragraph Font"]}"> KEY RESPONSIBLITIES:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Specifying design verification plan at soc level/IP level</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Specifying or reviewing verification plans for complex blocks within the ASIC</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">self-checking, reusable, automated verification environment : both at full-chip & block level</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Constrained random generators and reference models</li></ul></li><li style="margin-top: 0px;margin-right: 0px;margin-bottom: 0px;margin-left: 24px;padding-top: 0px;padding-right: 0px;padding-bottom: 0px;padding-left: 0px;font-size: 12pt;font-family: Arial, Arial_MSFontService, sans-serif;">Carve out the scope and work hands-on on functional verification.Guide/mentor junior members on the teamWork with internal/external stakholders to drive company-wide solutions</li></ul> PREFERRED EXPERIENCE:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Minimum 12+ years of experience in ASIC Design Verification</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Must have excellent knowledge of ASIC Design Flow and SOC architecture</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in developing complex testbench/model in verilog, System verilog or SystemC</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience with coverage-based verification methodology</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in writing testplans and testcases</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Excellent debug skills in functional simulations are must.</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in random test generation, coverage analysis, failure debug</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/shell scripts programming skills.</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="7" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1"> Must have very strong communication skills and the ability/desire to foster a team/global environment.</li></ul> ACADEMIC CREDENTIALS:<ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 11pt; font-family: Calibri, Calibri_MSFontService, sans-serif;" data-leveltext="" data-font="Symbol" data-listid="8" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="1" data-aria-level="1">Bachelors or Masters degree in computer engineering/Electrical Engineering<span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> </li></ul> <span style="margin: 0px; padding: 0px; font-size: 12pt; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif; color: #32363a;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}">#LI-PK2

Collected experience requirement

12+ years