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Lead CPU Design Verification Engineer

AMD · Hyderabad

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Employer requisition: 89899

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Collected role description

<strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><strong><span style="font-family: 'Arial',sans-serif;">ADVANCE YOUR CAREER. ADVANCE THE WORLD.</span></strong></span></p><p style="margin: 0px;"><span style="font-family: Arial, sans-serif; font-size: 12pt;">At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.</span></p><p style="margin: 0px;"><span style="font-family: Arial, sans-serif; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-family: Arial, sans-serif; font-size: 12pt;">AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.</span></p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">THE ROLE:</span></strong></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">The Core design and verification team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">THE PERSON:</span></strong></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">KEY RESPONSIBILITIES:</span></strong></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Verification of high performance x86-core ISA features</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor.</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Strong understanding of low power verification flows</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Development of detailed test plans and driving the execution of test plan, including functional coverage. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Understanding the existing test bench setup and look for opportunities to improve the existing test bench. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Adhering to coding guideline practices, develop and implement code review process. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Collaborate with global design verification teams and drive effectively the execution of the verification plans. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.</span></li></ul><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></strong></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">PREFERRED EXPERIENCE:</span></strong></p><ul><li style="margin-left: .25in;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">ASIC design verification experience 8 to 12 years. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Strong understanding the design and verification life cycle.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Hands on verification experience with C/C++/SystemVerilog testbench development. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Hands on experience with coverage planning, coding and coverage closure. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience with x86, ARM or any other industry standard microprocessor ISA.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience with Cache, Coherency and Data-Consistency verification. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience in clocking, reset, power-up sequences and power management verification. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Understanding of low power design verification techniques is a plus. </span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif; color: black;">ACADEMIC CREDENTIALS:</span></strong></p><ul><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">#LI-BM2 </span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;"> </span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">LOCATION:</span></strong></p><p style="margin: 0px;">Bangalore</p> <br><strong class="jdheading"></strong><br><br><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described: </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;"> </span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;"> </span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected minimum qualification

<p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">Benefits offered are described:&nbsp; </span></em><span style="font-family: 'Arial',sans-serif; color: black;"><a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>.</span></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.&nbsp;&nbsp; We encourage applications from all qualified candidates and will accommodate applicants&rsquo; needs under the respective laws throughout all stages of the recruitment and selection process.</span></em></span></p><p style="margin: 0px;"><span style="color: black; font-size: 12pt;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.&nbsp; AMD&rsquo;s &ldquo;Responsible AI Policy&rdquo; is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a></span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">&nbsp;</span></em></span></p><p style="margin: 0px;"><span style="font-size: 12pt;"><em><span style="font-family: 'Arial',sans-serif; color: black;">This posting is for an existing vacancy.</span></em></span></p>

Collected preferred qualification

<p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">THE ROLE:</span></strong></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">The Core design and verification team is responsible for development of &lsquo;High performance and Ultralow power x86 microprocessor core&rsquo;. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">THE PERSON:</span></strong></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Candidates should have solid track record of working on complex designs with hands on experience on architecting and developing test-bench, test-bench components, test-planning and execution of testplan, coverage development and closure. Candidate should have working experience with global teams spread across different geography and time-zones. </span></p><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">KEY RESPONSIBILITIES:</span></strong></p><ul style="margin-top: 0in;"><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Verification of high performance x86-core ISA features</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Architecting and development of testbench, test-bench components for high performance Cache, x86 ISA features, clock/reset/power features of processor.</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Strong understanding of low power verification flows</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Development of detailed test plans and driving the execution of test plan, including functional coverage. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Understanding the existing test bench setup and look for opportunities to improve the existing test bench. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Adhering to coding guideline practices, develop and implement code review process. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Collaborate with global design verification teams and drive effectively the execution of the verification plans. </span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.</span></li></ul><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></strong></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">PREFERRED EXPERIENCE:</span></strong></p><ul><li style="margin-left: .25in;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">ASIC design verification experience 8 to 12 years. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Strong understanding the design and verification life cycle.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Hands on verification experience with C/C++/SystemVerilog testbench development. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Hands on experience with coverage planning, coding and coverage closure. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience with x86, ARM or any other industry standard microprocessor ISA.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience with Cache, Coherency and Data-Consistency verification. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Experience in clocking, reset, power-up sequences and power management verification. </span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Knowledge of microprocessor design-for-debug (DFD) logic will be a plus.</span></li><li style="margin-left: .25in;"><span style="font-family: 'Calibri Light',sans-serif; color: black;">Understanding of low power design verification techniques is a plus. </span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif; color: black;">ACADEMIC CREDENTIALS:</span></strong></p><ul><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">Master&rsquo;s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture</span></li><li><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">#LI-BM2&nbsp;</span></li></ul><p style="margin: 0px;"><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">&nbsp;</span></p><p style="margin: 0px;"><strong><span style="font-size: 11.0pt; font-family: 'Calibri Light',sans-serif;">LOCATION:</span></strong></p><p style="margin: 0px;">Bangalore</p>

Collected experience requirement

8-12 years