Product Application Engineer - Run-Time Reconfiguration

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 89230

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. <h2>THE ROLE</h2>The Technical Marketing Engineer for AMD-AECG is an adaptable, self-motivated individual who drives the Vivado and next-generation tool product roadmap to best serve customer needs. This role is responsible for feature specification, planning, validation, documentation, early training materials, and key customer support. Technical Marketing works closely with Product Planning, R&D, Applications Engineering, and top-tier customers to improve the FPGA and Adaptive SoC design process and enable next-generation designs and methodologies. The environment is fast-paced, global, and focused on emerging technologies.<h2>THE PERSON</h2>The successful Technical Marketing Engineer plays a critical role in defining, planning, and supporting Run-Time Reconfiguration (RTR) flows in the Vivado Design Suite for AMD FPGA and Adaptive SoC products. This includes maintaining Run-Time Reconfiguration Intellectual Property (IP), enabling advanced use cases that reduce compile time, ensuring compliance with PCI Express standards, and driving the next generation of the Vivado tool roadmap.This individual understands customer requirements and pain points across Run-Time Reconfiguration, design partitioning, module reuse, and preservation-based incremental compilation flows, and translates those insights into innovative product capabilities. The ability to manage multiple priorities and collaborate across global teams is essential. We operate with an agentic, AI-first mindset and expect team members to actively incorporate AI into how they work.<h2>KEY RESPONSIBILITIES</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define best-in-class development flows, features, and methodologies for Run-Time Reconfiguration across AMD FPGA, Zynq™, and Adaptive SoC tools and libraries.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive Run-Time Reconfiguration, design partitioning, module-level reuse, and compile-time reduction methodologies from feature specification through validation.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Maintain and enhance Run-Time Reconfiguration IP and associated tool flows to support advanced customer use cases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with Engineering, Product Planning, Sales, and customers to define and deliver innovative tool features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Provide technical expertise to field teams and customers by developing training materials, tutorials, application notes, and user guides.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Communicate complex technical concepts clearly to internal stakeholders and customers, including architecture, implementation tradeoffs, and design recommendations.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Gather and analyze customer and field feedback, identify opportunities for new features and product improvements, and work closely with Planning and Engineering teams to drive implementation.</li></ul><h2>PREFERRED EXPERIENCE</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong knowledge of the complete FPGA design flow and Vivado tool suite.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Hands-on experience with Run-Time Reconfiguration or similar modular and reconfigurable design methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understanding of design partitioning, module reuse, incremental compilation, and preservation-based implementation flows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expertise in System-on-Chip (SoC) development.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience applying AI/ML technologies, including AI-assisted design, automation, debug, or agentic engineering workflows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Demonstrated ability to analyze and solve complex system-level technical challenges, both independently and in collaboration with strategic customers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent written, verbal, and presentation communication skills.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proven ability to collaborate effectively with geographically distributed, cross-functional teams.</li></ul>#LI-NS2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<h2>THE ROLE</h2>The Technical Marketing Engineer for AMD-AECG is an adaptable, self-motivated individual who drives the Vivado and next-generation tool product roadmap to best serve customer needs. This role is responsible for feature specification, planning, validation, documentation, early training materials, and key customer support. Technical Marketing works closely with Product Planning, R&D, Applications Engineering, and top-tier customers to improve the FPGA and Adaptive SoC design process and enable next-generation designs and methodologies. The environment is fast-paced, global, and focused on emerging technologies.<h2>THE PERSON</h2>The successful Technical Marketing Engineer plays a critical role in defining, planning, and supporting Run-Time Reconfiguration (RTR) flows in the Vivado Design Suite for AMD FPGA and Adaptive SoC products. This includes maintaining Run-Time Reconfiguration Intellectual Property (IP), enabling advanced use cases that reduce compile time, ensuring compliance with PCI Express standards, and driving the next generation of the Vivado tool roadmap.This individual understands customer requirements and pain points across Run-Time Reconfiguration, design partitioning, module reuse, and preservation-based incremental compilation flows, and translates those insights into innovative product capabilities. The ability to manage multiple priorities and collaborate across global teams is essential. We operate with an agentic, AI-first mindset and expect team members to actively incorporate AI into how they work.<h2>KEY RESPONSIBILITIES</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define best-in-class development flows, features, and methodologies for Run-Time Reconfiguration across AMD FPGA, Zynq™, and Adaptive SoC tools and libraries.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive Run-Time Reconfiguration, design partitioning, module-level reuse, and compile-time reduction methodologies from feature specification through validation.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Maintain and enhance Run-Time Reconfiguration IP and associated tool flows to support advanced customer use cases.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with Engineering, Product Planning, Sales, and customers to define and deliver innovative tool features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Provide technical expertise to field teams and customers by developing training materials, tutorials, application notes, and user guides.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Communicate complex technical concepts clearly to internal stakeholders and customers, including architecture, implementation tradeoffs, and design recommendations.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Gather and analyze customer and field feedback, identify opportunities for new features and product improvements, and work closely with Planning and Engineering teams to drive implementation.</li></ul><h2>PREFERRED EXPERIENCE</h2><ul><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong knowledge of the complete FPGA design flow and Vivado tool suite.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Hands-on experience with Run-Time Reconfiguration or similar modular and reconfigurable design methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Understanding of design partitioning, module reuse, incremental compilation, and preservation-based implementation flows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expertise in System-on-Chip (SoC) development.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience applying AI/ML technologies, including AI-assisted design, automation, debug, or agentic engineering workflows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Demonstrated ability to analyze and solve complex system-level technical challenges, both independently and in collaboration with strategic customers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent written, verbal, and presentation communication skills.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proven ability to collaborate effectively with geographically distributed, cross-functional teams.</li></ul>#LI-NS2