Product Application Engineer - Debug

AMD · Hyderabad

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Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 89229

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. <h2>THE ROLE</h2>The Technical Marketing Engineer for AMD-AECG is an adaptable, self-motivated individual who drives the Vivado and next-generation tool product roadmap to best serve customer needs. This role is responsible for feature specification, planning, validation, documentation, early training materials, and key customer support. Technical Marketing works closely with Product Planning, R&D, Applications Engineering, and top-tier customers to improve the FPGA and Adaptive SoC design process and enable next-generation designs and methodologies. The environment is fast-moving, global, and focused on emerging technologies.<h2>THE PERSON</h2>The successful Technical Marketing Engineer plays a critical role in defining, planning, and supporting Programming File Generation and Hardware Debug in the Vivado Design Suite for AMD FPGA and Adaptive SoC products. This includes driving the programming file generation flow and the in-system debug experience through Vivado Hardware Manager, Integrated Logic Analyzer (ILA), Virtual I/O (VIO), and readback/verification.This person understands customer needs and pain points across bring-up and silicon debug, and helps define the next generation of the tool roadmap. The ability to manage competing priorities is essential. We operate with an agentic, AI-first mindset and expect team members to actively incorporate AI into how they work.<h2>KEY RESPONSIBILITIES</h2><ul data-spread="false"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define best-in-class programming file generation and hardware debug flows, features, and methodologies for AMD FPGA, Zynq, and Adaptive SoC tools and libraries.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive the programming file generation flow and in-system debug capabilities, including Hardware Manager, ILA, VIO, and readback, from specification through validation.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Lead field escalation response for critical debug and programming tool failures in production environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Own toolchain integration with third-party development and production test environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with R&D on new device support and bring-up validation for debug and programming tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Partner with Engineering, Sales, Planning, and Customers to define and deliver tool features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Provide technical expertise to the field and customers through training materials, tutorials, and user guides, and mentor Field Applications Engineers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Communicate complex topics clearly to field teams and customers, including options, tradeoffs, and impact.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Evaluate field and customer feedback, identify high-priority feature gaps and improvements, and work with Planning and Engineering to drive fixes.</li></ul><h2>PREFERRED EXPERIENCE</h2><ul data-spread="false"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong knowledge of the full FPGA design process and tool flow.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Working knowledge of programming file generation and in-system hardware debug flows, including ILA/VIO and readback, or similar methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with field escalations, toolchain integration, and production test environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expertise in system-on-chip development.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience applying AI/ML tools and techniques, such as AI-assisted design, debug, automation, or agentic workflows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to analyze and solve complex system-level issues, independently and in collaboration with top-tier customers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent written communication and presentation skills.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proven ability to collaborate effectively with global teams</li></ul> #LI-NS2 Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<h2>THE ROLE</h2>The Technical Marketing Engineer for AMD-AECG is an adaptable, self-motivated individual who drives the Vivado and next-generation tool product roadmap to best serve customer needs. This role is responsible for feature specification, planning, validation, documentation, early training materials, and key customer support. Technical Marketing works closely with Product Planning, R&D, Applications Engineering, and top-tier customers to improve the FPGA and Adaptive SoC design process and enable next-generation designs and methodologies. The environment is fast-moving, global, and focused on emerging technologies.<h2>THE PERSON</h2>The successful Technical Marketing Engineer plays a critical role in defining, planning, and supporting Programming File Generation and Hardware Debug in the Vivado Design Suite for AMD FPGA and Adaptive SoC products. This includes driving the programming file generation flow and the in-system debug experience through Vivado Hardware Manager, Integrated Logic Analyzer (ILA), Virtual I/O (VIO), and readback/verification.This person understands customer needs and pain points across bring-up and silicon debug, and helps define the next generation of the tool roadmap. The ability to manage competing priorities is essential. We operate with an agentic, AI-first mindset and expect team members to actively incorporate AI into how they work.<h2>KEY RESPONSIBILITIES</h2><ul data-spread="false"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Define best-in-class programming file generation and hardware debug flows, features, and methodologies for AMD FPGA, Zynq, and Adaptive SoC tools and libraries.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Drive the programming file generation flow and in-system debug capabilities, including Hardware Manager, ILA, VIO, and readback, from specification through validation.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Lead field escalation response for critical debug and programming tool failures in production environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Own toolchain integration with third-party development and production test environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Collaborate with R&D on new device support and bring-up validation for debug and programming tools.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Partner with Engineering, Sales, Planning, and Customers to define and deliver tool features.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Provide technical expertise to the field and customers through training materials, tutorials, and user guides, and mentor Field Applications Engineers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Communicate complex topics clearly to field teams and customers, including options, tradeoffs, and impact.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Evaluate field and customer feedback, identify high-priority feature gaps and improvements, and work with Planning and Engineering to drive fixes.</li></ul><h2>PREFERRED EXPERIENCE</h2><ul data-spread="false"><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Strong knowledge of the full FPGA design process and tool flow.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Working knowledge of programming file generation and in-system hardware debug flows, including ILA/VIO and readback, or similar methodologies.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience with field escalations, toolchain integration, and production test environments.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Expertise in system-on-chip development.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Experience applying AI/ML tools and techniques, such as AI-assisted design, debug, automation, or agentic workflows.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Ability to analyze and solve complex system-level issues, independently and in collaboration with top-tier customers.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Excellent written communication and presentation skills.</li><li style="font-family: arial, helvetica, sans-serif; font-size: 12pt;">Proven ability to collaborate effectively with global teams</li></ul> #LI-NS2