Lead DFT Engineer

AMD · Bangalore

Source and collection record

Last observed by our collector: 9 October 2026 at 12:45 am IST. This is not a manual review or a confirmation from the employer.

Employer requisition: 88741

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Collected minimum qualification: Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.Attendance and availability: I checked the employer page for work location, office attendance, start date and duration.Current requisition: I checked the current employer requisition and its application requirements.

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Collected role description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them. AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward. <span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">Lead DFT Engineer: <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif; font-weight: bold;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1">THE ROLE:</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1">As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the DFT Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success. THE PERSON:The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with 7+ Years of Strong understanding on Scan Architecture and Scan features </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">GLS, Timing and Power Aware Simulations</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Test coverage and test cost reduction analysis </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Yield Analysis & Debug for Design root cause & Recovery</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Post Silicon Bring Up: Planning, Co-ordination, and Execution</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">DFT Silicon bring up expertise from across tech various nodes</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Extensive Silicon Debug for Phasing closure and production enablement</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups</li></ul> PREFERRED EXPERIENCE:<ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design </li></ul> ACADEMIC CREDENTIALS: <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering </li></ul> </li><li>#LI-SR5</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </li></ul> Benefits offered are described: <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected minimum qualification

Benefits offered are described:  <a href="https://www.amd.com/en/corporate/careers/benefits.html" target="_blank" rel="noopener">AMD benefits at a glance</a>. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available <a href="https://www.amd.com/en/legal/responsible-ai-use-policy.html" target="_blank" rel="noopener">here.</a> This posting is for an existing vacancy.

Collected preferred qualification

<span style="margin: 0px; padding: 0px;" data-ccp-charstyle="normaltextrun" data-ccp-charstyle-defn="{"ObjectId":"75ee5cbf-7016-4753-9550-8bbf976473cd|105","ClassId":1073872969,"Properties":[469775450,"normaltextrun",201340122,"1",134233614,"true",469778129,"normaltextrun",335572020,"1",469778324,"Default Paragraph Font"]}">Lead DFT Engineer: <span style="margin: 0px; padding: 0px; font-family: Arial, Arial_EmbeddedFont, Arial_MSFontService, sans-serif;" data-ccp-props="{"134233117":false,"134233118":false,"201341983":0,"335559738":0,"335559739":0,"335559740":240}"> <ul style="margin: 0px; padding: 0px; font-family: verdana;"><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif; font-weight: bold;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1">THE ROLE:</li><li style="margin: 0px 0px 0px 24px; padding: 0px; font-size: 12pt; font-family: 'Times New Roman', 'Times New Roman_MSFontService', serif;" data-leveltext="" data-font="Symbol" data-listid="11" data-list-defn-props="{"335552541":1,"335559684":-2,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" aria-setsize="-1" data-aria-posinset="3" data-aria-level="1">As a member of the AMD, you will help bring to life cutting-edge designs. As a member of the DFT team, you will work closely with the DFT Architecture, IP design, Physical Design teams, and Product Engineers to achieve first pass silicon success. THE PERSON:The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with 7+ Years of Strong understanding on Scan Architecture and Scan features </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Scan insertion and ATPG pattern generation for Stuck at, Transition ATPG, IDDQ Pattern Generation</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">GLS, Timing and Power Aware Simulations</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Test coverage and test cost reduction analysis </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Yield Analysis & Debug for Design root cause & Recovery</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Post Silicon Bring Up: Planning, Co-ordination, and Execution</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">DFT Silicon bring up expertise from across tech various nodes</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Extensive Silicon Debug for Phasing closure and production enablement</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience of multiple SOC Tape-Outs and Post Silicon Bring-ups</li></ul> PREFERRED EXPERIENCE:<ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX </li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design </li></ul>  ACADEMIC CREDENTIALS:  <ul style="margin-top: 0in; margin-bottom: 0in;" type="disc"><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;">Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering </li></ul>  </li><li>#LI-SR5</li><li style="margin-top: 0in; margin-right: 0in; margin-bottom: 0in; font-size: 12pt; font-family: Aptos, sans-serif;"> </li></ul>

Collected experience requirement

7+ years